Seong Jin Jang

A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

For operating frequencies exceeding 500 MHz, the timing margin of the I/O interface is critical and requires the data input-output timing accuracy to be within 200 ps. To meet the requirement, the designed SDRAM adopts a digitally self-calibrated on-die-termination with linearity error of /spl plusmn/1% and achieves over 1.2 Gbps/pin stable operation by using window matching and latency control. The chip is fabricated in a 0.13 /spl mu/m triple-well DRAM process.

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Technology scaling has continuously improved the density, performance, energy efficiency, and cost of DRAM-based main memory systems. Starting from sub-20nm processes, however, the industry began to pay considerably higher costs to screen and manage notably increasing defective cells. The traditional technique, which replaces the rows/columns containing faulty cells with spare rows/columns, has been able to cost-effectively repair the defective cells so far, but it will become unaffordable soon because an excessive number of spare rows/columns are required to manage the increasing number of defective cells. This necessitates a synergistic application of an alternative resilience technique such as In-DRAM ECC with the traditional one. Through extensive measurement and simulation, we first identify that aggressive miniaturization makes DRAM cells more sensitive to random telegraph noise or variable retention time, which is dominantly manifested as a surge in randomly scattered single-cell faults. Second, we advocate using In-DRAM ECC to overcome the DRAM scaling challenges and architect In-DRAM ECC to accomplish high area efficiency and minimal performance degradation. Moreover, we show that advancement in process technology reduces decoding/correction time to a small fraction of DRAM access time, and that the throughput penalty of a write operation due to an additional read for a parity update is mostly overcome by the multi-bank structure and long burst writes that span an entire In-DRAM ECC codeword. Lastly, we demonstrate that system reliability with modern rank-level ECC schemes such as single device data correction is further improved by hundred million times with the proposed In-DRAM ECC architecture.

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

A highly reliable antifuse cell and its sensing scheme that can be actually adopted in DRAM are presented. A multi-cell structure is newly devised to circumvent the large process variation problems of the DRAM cell capacitor type antifuse system. The programming current is less than 564µA up to the nine-cell case. The experimental results show that the cumulative distribution of the successful rupture in multi-cell structure is dramatically enhanced to be less than 15% of single-cells case and the recovery problem of the programmed cell after the thermal stress (300°C) is disappeared. In addition, also presented is a Post-Package Repair (PPR) scheme that is directly coupled to external power using additional pin for the requisite high voltage with protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1Gbit DDR SDRAM is fabricated using Samsungs advanced 50nm DRAM process technology, successfully showing the feasibility of the proposed antifuse system implemented in it.