In-Dal Song

Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates

This paper reports on new concept consisting of all-oxide-based device component for future high density non-volatile data storage with stackable structure. We demonstrate a GaInZnO (GIZO) thin film transistors (TFTs) integrated with 1D (CuO/InZnO)-1R (NiO) (one diode-one resistor) structure oxide memory node element. RRAM (Resistance Random Access Memory) has provided advantages in fabrication which have made these works possible. Therefore we also suggest methods and techniques for improving the distribution in bi-stable resistance characteristics of the NiO memory node. In order to fabricate stack structures, all device fabrication steps must be possible at low temperatures. The benefits provided by low temperature processes are demonstrated by our devices fabricated over glass substrates. Our paper shows the device characteristics of each individual component as well as the characteristics of combined select transistor with 1D-1R cell. XPS analysis of NiO RRAM resistance layer deposited by ALD confirms similar conclusions to previous reports of the importance of metallic Ni content in sputtered NiO for bistable resistance switching. Also we herein propose a generalized stacked-memory structure to minimize on-chip real estate to maximize integrated density.

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open drain I/O interface, and data rate increase from 1.6 to 3.2Gb/s. To achieve high performance at low supply voltage and reduce power consumption, this work introduces new functions and describes their implementation. Data bus inversion (DBI) is employed for high-speed transactions to reduce power consumption of I/O and SSN noise. Dual-error detection, which adopts cyclic redundancy check (CRC) for DQ, and command address (CA) parity is designed to guarantee reliable transmission. GDDR5 memory also has DBI and CRC functions [1], but in this work, these schemes are implemented in a way that reduces area overhead and timing penalty. Besides these error-check functions, an enhanced gain buffer and a PVT-tolerant fetch scheme improve basic receiving ability. To meet the output jitter requirements of DDR4 SDRAM, the type of delay line for DLL is selected at initial stage according to data rate.

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

For the demand of sever systems with high performance, high density and low power consumption, 3-D DDR4 SDRAM with TSVs was developed. In order to achieve higher data rate at lower voltage in comparison with precedent DDR3 SDRAM with TSVs, the placements of TSVs have been optimized without the penalty of chip size and the calibration method for reducing process mismatch between stacked DRAM chips is proposed. Additionally, new cell test method for stacked dies is adopted to keep costs down and the skewed self-refresh is proposed to reduce power noise. The IO speed of new DDR4 SDRAM with TSVs is increased to 2.4Gb/s at 1.2V.

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

As the demand for high-frequency DDR SDRAM increases, duty-cycle correction circuits (DCC) become a key element to widen the data-valid window (tDV). For duty detection in a DCC, analog schemes using charge pumps [1] and digital schemes using DLL locking [2] or time-to-digital converters (TDC) [3] are widely used. However, they require a certain amount of time proportional to duty errors or a high-resolution TDC to resolve quantization errors. For correction, an edge combiner or slew-rate-changing inverter is commonly used in DRAM applications. An edge combiner utilizes 180°-phase-shifted clocks, which are obtained by DLL locking or TDC code calculation [4-5], to generate both edges, but it has high-frequency limitations due to gate-delay-based short-pulse generation. The slew-rate-changing inverter has trade-offs between range and resolutions or between resolutions and DCC locking time. To achieve both wide range and fast locking, asynchronous binary search for detection and receiver tail-current tuning can be used for correction [6]. In a WCK-based system, duty and phase skew between iclk and qclk are related to the detection range. However, for normal DDR DRAM, this range should be doubled resulting in more area as well as locking time. To resolve problems with locking time, coverage, and resolution, a hybrid DCC is presented in this paper. For precise duty error detection, the phase and DCC locking processes should be separated, because delay updating disturbs duty-error detecting and averaging. In this paper, an all-digital DCC with TDC and an enhanced edge combiner performs fast DCC operation before DLL coarse locking, and a slew-rate-changing DCC optimized for fine resolution compensates quantization errors caused by all-digital operation.

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.