Chi Yaqing

Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

Heavy ion experiments on 65 nm bulk CMOS inverter chains demonstrate the impact of circuit placement on single-event transients (SETs). Experimental data and simulations show that the horizontal placement design significantly reduces the SET pulse width and SET cross-section compared to the vertical placement design due to the existence of pulse quenching.

PABAM: A Physics-Based Analytical Model to Estimate Bipolar Amplification Effect Induced Collected Charge at Circuit Level

This paper presents a physics-based analytical model called PABAM. It is performed to estimate the bipolar amplification effect induced collected charge at circuit level. The PABAM is validated by TCAD simulation with different technologies and layout parameters. The collected charge obtained from combining the PABAM and the diffusion-collection model agrees well with TCAD simulation results, both in magnitude and trend. The proposed PABAM is implemented in the circuit-level SER prediction approach to evaluate SEU for twin- and triple-well SRAMs. The simulated cross sections have a good agreement with heavy ion experimental data, particularly for MCU prediction.

Mechanism of single-event transient pulse quenching between dummy gate isolated logic nodes*

As integrated circuits scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes. The so-called single-event transient (SET) pulse quenching induced by single-event charge sharing collection has been widely studied. In this paper, SET pulse quenching enhancement is found in dummy gate isolated adjacent logic nodes compared with that isolated by the common shallow trench isolation (STI). The physical mechanism is studied in depth and this isolation technique is explored for SET mitigation in combinational standard cells. Three-dimensional (3D) technology computer-aided design simulation (TCAD) results show that this technique can achieve efficient SET mitigation.

Confinement of gold quantum dot arrays inside ordered mesoporous silica thin film

Periodic disposed quantum dot arrays are very useful for the large scale integration of single electron devices. Gold quantum dot arrays were self-assembled inside pore channels of ordered amino-functionalized mesoporous silica thin films, employing the neutralization reaction between chloroauric acid and amino groups. The diameters of quantum dots are controlled via changing the aperture of pore channels from 2.3 to 8.3 nm, which are characterized by HRTEM, SEM and FT-IR. UV-vis absorption spectra of gold nanoparticle/mesoporous silica composite thin films exhibit a blue shift and intensity drop of the absorption peak as the aperture of mesopores decreases, which represents the energy level change of quantum dot arrays due to the quantum size effect.

Comparison of radiation-induced charge sharing generated by heavy ion and pulsed laser

Charge sharing induced SEU and SEMT are investigated using heavy ion and pulsed laser. Measurement results are compared and it indicates pulsed laser could generate charge sharing similar to heavy ion. 3D-TCAD simulation is performed to investigate the factors to impact on pulsed laser induced chare sharing. Simulation results show that the beam spot size impact on charge sharing in the high laser energy while the variation of the calculated equivalent LET impact on charge sharing in the low laser energy.

Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies

As chip technologies scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes. The so-called pulse quenching effect, induced by single-event charge sharing collection, has been widely explored in efforts to find mitigation techniques for single-event transients (SETs) or single-event upsets (SEUs), and the dummy gate isolation has been proven to be an efficient layout technique for pulse quenching enhancement. In this paper, the characterization of SET pulse quenching among dummy gate isolated logic nodes is performed in 65 nm twin-well and triple-well CMOS technologies. Four groups of heavy ion experiments are explored for the characterization, and the pulse quenching effect is quantitatively analyzed in detail. The pulse quenching effects show different characteristics in twin-well and triple-well CMOS technologies.

Impact of substrate injected hot electrons on hot carrier degradation in a 180-nm NMOSFET

Although hot carriers induced degradation of NMOSFETs has been studied for decades, the role of hot electron in this process is still debated. In this paper, the additional substrate hot electrons have been intentionally injected into the oxide layer to analyze the role of hot electron in hot carrier degradation. The enhanced degradation and the decreased time exponent appear with the injected hot electrons increasing, the degradation increases from 21.80% to 62.00% and the time exponent decreases from 0.59 to 0.27 with Vb decreasing from 0 V to −4 V, at the same time, the recovery also becomes remarkable and which strongly depends on the post stress gate bias Vg. Based on the experimental results, more unrecovered interface traps are created by the additional injected hot electron from the breaking Si–H bond, but the oxide trapped negative charges do not increase after a rapid recovery.