Chen Shuming

Temperature Dependence of Digital SET Pulse Width in Bulk and SOI Technologies

Using three-dimensional mixed-mode simulation, temperature dependence of digital SET pulse width in bulk and PD SOI inverter chains has been studied. It was found that temperature has a very important impact on digital SET. Using a LET of 60 MeVmiddotcm2 /mg, when temperature rises from -55 to 125degC , the digital SET pulse width in bulk and floating SOI inverter chains rises remarkably, while in a SOI inverter chain with ideal body tie, the digital SET pulse width is almost constant with rising temperature. Detailed analysis showed that pulse broadening with rising temperature is primarily due to enhancement of bipolar amplification.

Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

Heavy ion experiments on 65 nm bulk CMOS inverter chains demonstrate the impact of circuit placement on single-event transients (SETs). Experimental data and simulations show that the horizontal placement design significantly reduces the SET pulse width and SET cross-section compared to the vertical placement design due to the existence of pulse quenching.

The Effect of Re-Convergence on SER Estimation in Combinational Circuits

Detailed analysis is presented on the effect of re-convergence on SER estimation in combinational circuits. The results show that the ignoring of re-convergence by previous independent pulse methods introduces significant errors in SER results. Furthermore, independent pulse methods miscalculate the SET sensitive nodes, leading to improper hardening strategy.

Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells

In this study, we investigated the impact of pulse quenching effect on the soft error vulnerabilities in combinational circuits. Simulation results illustrate that soft error vulnerabilities could be reduced by 4–16% for the benchmark circuits when the pulse quenching effect is introduced. By adjusting the cell orientations of the quenching cells in the layout, the soft error vulnerabilities could be further reduced. It is suggested that new placement algorithm considering circuit reliability should be designed to reduce the circuit soft error vulnerabilities. & 2012 Elsevier Ltd. All rights reserved.

Simulation Study of the Selectively Implanted Deep-N-Well for PMOS SET Mitigation

In this paper, a novel well structure for PMOS single-event transient (SET) mitigation is studied by way of technology computer-aided design (TCAD) numerical simulations. Based on a 90-nm CMOS technology, the simulation results show that the proposed selectively implanted deep-N-well (SIDNW) can significantly reduce the SET pulsewidth without area, power, and performance overheads, when compared with the conventional dual-well process. A comparison is also made with the triple-well process.

Novel N-hit single event transient mitigation technique via open guard transistor in 65 nm bulk CMOS process

In this paper, we proposed a new n-channel MOS single event transient (SET) mitigation technique, which is called the open guard transistor (OGT) technique. This hardening scheme is compared with several classical n-channel MOS hardening structures through 3-D TCAD simulations. The results show that this scheme presents about 35% improvements over the unhardened scheme for mitigating the SET pulse, and its upgrade, the 2-fringe scheme, takes on even more than 50% improvements over the unhardened one. This makes significant sense for the semi-conductor device reliability.

A novel layout for single event upset mitigation in advanced CMOS SRAM cells

A novel layout has been proposed to reduce the single event upset (SEU) vulnerability of SRAM cells. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors. For the angle incidence, the proposed layout is immune from ion hit in two plans, and is more robust against SEU in other two plans than the conventional one. The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%. Consequently, the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

The effect of P + deep well doping on SET pulse propagation

The change of P+ deep well doping will affect the charge collection of the active and passive devices in nano-technology, thus affecting the propagated single event transient (SET) pulsewidths in circuits. The propagated SET pulsewidths can be quenched by reducing the doping of P+ deep well in the appropriate range. The study shows that the doping of P+ deep well mainly affects the bipolar amplification component of SET current, and that changing the P+ deep well doping has little effect on NMOS but great effect on PMOS.

Recovery of single event upset in advanced complementary metal—oxide semiconductor static random access memory cells

Using computer-aided design three-dimensional (3D) simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer (LET) threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability.

Hot carrier effects of SOI NMOS

Hot carrier effect (HCE) is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS. Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation, a HCE degradation model for annular NMOS and two-edged NMOS is proposed. According to this model, we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate, and annular NMOS has more serious HCE degradation than two-edged NMOS. The design, fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.