Chia-Hao Hsu

A reconfigurable 16-channel HV stimulator ASIC for Spinal Cord Stimulation systems

A 16-channel stimulation waveform generator ASIC using high voltage CMOS technology to generate high voltage stimulation signals for Spinal Cord Stimulation (SCS) systems is presented in this study. To enlarge the voltage swing on high-impedance electrodes, the output stage of the proposed for the SCS systems is implemented on silicon using a 0.25 μm high-voltage (60 V) devices. Particularly, a charge pump composed of 5 cascaded voltage doublers is used to boost the core voltage (2.5 V) to higher than 10 V required by the SCS systems to execute electrical stimulation therapy [1]. A total of 16 stimulation waveform generators are included to drive 16 sets of electrodes, where each generator is composed of an HV operational amplifier and an HV analog switch. Compared with existing commercial products, the proposed SCS system attains better flexibility to meet the spinal cord stimulation high voltage demand in addition to the reduction of cost and PCB size.

A frequency-shift readout system for FPW allergy biosensor

In this paper, an IgE antigen concentration measurement system using a frequency-shift readout method for a two-port FPW (flexural plate-wave) allergy biosensor is presented. The proposed frequency-shift readout method adopts a peak detecting scheme to detect the resonant frequency. A linear frequency generator, a pair of peak detectors, two registers, and an subtractor are only needed in our system. According to the specification of the FPW allergy biosensor, the frequency sweep range is limited in 2 MHz to 10 MHz. The sensitivity of the peak detector is 0.8 mV. The proposed frequency-shift readout circuit is verified on silicon by using a standard 0.18 µm CMOS technology. The maximal power consumption is 12.94 mW@0.1 MHz clock given by HSPICE simulations.

A one-time implantable wireless power bidirectional transmission spinal cord stimulation system

This study presents a prototype of a one-time implantable spinal cord stimulation system (SCS) using wireless power and bidirectional data transmission by an inductive link. The data can be transmitted by an inductive link, which is based on a duplex ASK-LSK technique. A fabrication chip is integrated in the bio-implant to generate stimulation waveform control signals. The chip area is 1800 × 1250 µm2. The proposed SCS system attain better flexibility of operation modes than that of a commercial product, i.e., Medtronic Itrel 3 7425.

A Protein Concentration Measurement System Using a Flexural Plate-Wave Frequency-Shift Readout Technique

A protein concentration measurement system with two-port flexural plate-wave (FPW) biosensors using a frequency-shift readout technique is presented in this paper. The proposed frequency-shift readout method employs a peak detecting scheme to measure the amount of resonant frequency shift. The proposed system is composed of a linear frequency generator, a pair of peak detectors, two registers, and a subtractor. The frequency sweep range of the linear frequency generator is limited to 2 MHz to 10 MHz according to the characteristics of the FPW biosensors. The proposed frequency-shift readout circuit is carried out on silicon using a standard 0.18 μm CMOS technology. The sensitivity of the peak detectors is measured to be 10 mV. The power consumption of the proposed protein concentration measurement system is 48 mW given a 0.1 MHz system clock.

Low power RC5 cipher for ZigBee portable biomedical systems

This paper presents a half-run RC5 cipher architecture with low power dissipation for transmission security of biomedical systems. The proposed architecture uses a resource-sharing approach utilizing only one adder/subtractor, one bi-directional barrel shifter, and one XOR with 32-bit bus width. Therefore, two data paths are switched through four multiplexers in the encryption/decryption procedure. A prototype chip is fabricated by a standard 0.18 μm CMOS technology. The size is 704∗697 μm2, where a total of 1.64k gates are used. The proposed architecture consumes 5.87 mW@50 MHz system clock.

Low-power 7.2 GHz complementary all-N-transistor logic using 90 nm CMOS technology

This paper proposed an complementary all-N-transistor (CANT) comprising ANT logic and inverted ANT logic. In ANT logics N-Block, the threshold voltage of the transistors is variable depending on the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-Block is increased to VDD-Vthn to enhance the operation speed. In the pre-charge phase, the bulk voltage of the transistors in the N-Block is dropped to almost 0 V such that the subthreshold leakage current is reduced. By utilizing such a variable bulk voltage scheme in the proposed complementary ANT (CANT) logic, a 32-bit CLA is designed using TSMC 90 nm CMOS process to verify the low power and high speed performance. The area of the proposed design is 0.0483 mm2 and the power dissipation is 102 mW given a 7.2 GHz clock at the worst PVT condition.

A ROM-less DDFS using a nonlinear DAC with an error compensation current array

This paper presents the architecture and the circuit implementation of a direct digital frequency synthesizer (DDFS) with error compensation. The straight line approximation method with a 10-bit amplitude resolution is adopted in this work. The proposed technique replaces conventual ROM-based methods with a nonlinear digital-to-analog converter (DAC) to generate the sinusoid. The overall power dissipation as well as hardware complexity can be significantly reduced. This proposed DDFS is implemented using a standard 0.35 mum CMOS technology. The maximum power dissipation is 3.37 mW at the clock rate of 250 MHz. The chip area is 2.04 mm2. The spurious free dynamic range (SFDR) is 63.22 dBc at a 3 MHz output.

A Signed Array Multiplier with Bypassing Logic

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.

A fast FPW allergy analyzer prototype for point of care (POC)

An IgE antigen concentration analyzer system using a pair of two-port FPW (flexural plate-wave) sensors is proposed in this paper. The proposed system utilizes a frequency-shift readout method based on a peak detecting scheme to measure the resonant frequency shift. The frequency-shift readout circuit is integrated on silicon composed of a linear frequency generator, two peak detectors, two registers, and a subtractor. The frequency sweep range is from in 0.5 MHz to 11.6 MHz according to the characteristics of the FPW allergy biosensor. The sensitivity of the peak detector is 5 mV. The proposed frequency-shift readout circuit is verified by a prototype on PCB, where the maximal power consumption is 54 mW@5 kHz clock.

A fast FPW-based protein concentration measurement system

A fast protein concentration measurement system with two-port FPW (flexural plate wave) biosensors using a frequency-shift readout technique is presented in this paper. The proposed frequency-shift readout method employs a peak detecting scheme to measure the amount of resonant frequency shift. The frequency sweep range of the linear frequency generator is limited in 2 MHz to 10 MHz according to the characteristics of the FPW biosensors. The proposed frequency-shift readout circuit is verified on silicon using a standard 0.18 μm CMOS technology. The power consumption of the proposed protein concentration measurement system is 48 mW given a 0.1 MHz system clock. The protein concentration measurement is read out in less than 10 minutes.