Gang-Neng Sung

A power-aware 2-dimensional bypassing multiplier using cell-based design flow

This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method in cell-based design flow. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Thorough cell-based design flow post-layout simulations show that the power delay product of the proposed 8times8 multiplier design is reduced by more than 13.8% compared to prior designs.

A Low-power Sensorless Inverter Controller of Brushless DC Motors

A low-power sensorless inverter controller is designed for brushless DC (BLDC) motors without using any Hall sensor. A back-EMF (back-electromotive force) estimation method is adopted to detect the commutation moment for rotation control of the brushless DC motors. The position of the rotor can be precisely estimated by measuring the back-EMF as well as the zero-crossing points. The proposed controller is low power and low cost because of not using expensive power consuming Hall sensors. The proposed sensorless inverter controller is integrated in a standard mixed-signal single-poly, and six metal 0.18-mum CMOS process.

A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems

This paper presents a high speed transceiver design with fault detection circuit compliant with FlexRay standards V2.1. An LVDS-like transmitter is utilized to drive the twisted pair of the bus. A current detector is included in the transceiver to detect the operating current so as to prevent over-current hazard. By contrast, a 3-comparator scheme is used to carry out the required bit-slicing and state recognition in the receiver of the bus. A bus line short-circuit detector is also included in the proposed receiver design.

A low-power transceiver design for FlexRay-based communication systems

This paper presents a FlexRay Transceiver (FRT) used in an in-vehicle network compliant with FlexRay physical layer standards. FlexRay is a new standard for data/signal communication among ECUs (electronic control unit) installed in a vehicle. FRT at least comprises two major blocks in the physical layer design: the data transmission block, i.e., Bus Driver (BD), which is used to generate signals on the bus and recognize the signal electrical characteristics on the bus; and the control block, i.e., Major Controller, which is in charge of data path, security, and safety. The proposed FRT design in this work is implemented using a typical [emailxa0protected] CMOS process. The total core area is 1.01x0.894mm^2 and the power consumption is 76.62mW at a 80MHz system clock.

Low-power 7.2 GHz complementary all-N-transistor logic using 90 nm CMOS technology

This paper proposed an complementary all-N-transistor (CANT) comprising ANT logic and inverted ANT logic. In ANT logics N-Block, the threshold voltage of the transistors is variable depending on the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-Block is increased to VDD-Vthn to enhance the operation speed. In the pre-charge phase, the bulk voltage of the transistors in the N-Block is dropped to almost 0 V such that the subthreshold leakage current is reduced. By utilizing such a variable bulk voltage scheme in the proposed complementary ANT (CANT) logic, a 32-bit CLA is designed using TSMC 90 nm CMOS process to verify the low power and high speed performance. The area of the proposed design is 0.0483 mm2 and the power dissipation is 102 mW given a 7.2 GHz clock at the worst PVT condition.

A Signed Array Multiplier with Bypassing Logic

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.

A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard

This paper presents a FlexRay Transceiver (FRT) with Bus Guardian (BG) used in an in-vehicle network compliance with FlexRay physical layer standards. FlexRay is a new standard for data/signal communication among electronic devices installed in a vehicle. The FRT includes two major parts in the physical layer design: the data transmission part, i.e., Bus Driver (BD), which is used to generate and recognize the electrical characteristics on the bus; the control part, including Bus Driver Controller and Bus Guardian (BG), which is in charge of data path, security, safety, and supervising Communication Controller (CC) in FlexRay communication systems. The proposed FRT with BG design in this work is implemented using a typical 0.18 μm CMOS process. The total core area is 0.88 × 0.84 mm2 and the power consumption is 53.04 mW at a 80 MHz system clock by physical on-silicon measurement.

Energy-Efficient Double-Edge Triggered Flip-Flop

This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-Vth transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-Vth transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-Vth scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy).

Engery-Efficient Double-Edge Triggered Flip-Flop Design

This paper presents a novel design for double-edge triggered flip-flops (DETFF). Detailed analysis of the transistors used in the DETFF was presented to find out those on the critical path. Therefore, the proposed DETFF employs low-Vth transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-Vth transistors can be resolved at the same time. The proposed DETFF, thus, fully utilizes the multi-V th scheme provided by advanced CMOS processes without paying the price of large area, slow clocking frequency, and poor noise immunity. The proposed design is implemented using TSMC 0.18 mum 1P6M CMOS process. Post-layout simulation results reveal that the proposed DETFF saves at least 33 % power and 39 % power-delay product (i.e., the dissipated energy) at all PVT (process, supply voltage, temperature) corners

A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers

This paper describes the design and implementation of a sequential access memory (SAM) in the OFDM demodulator of DVB-T receivers. The SAM decoder is based upon a ring counter to reduce the transistor count as well as the number of transitions per memory access. The SAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. The power consumption of memory access is then reduced. A 2-Kb SAM is carried out by 0.18 mum 1P6M CMOS process to verify the proposed design. The average power dissipation of the address decoder is 41.97 muW, while the average power dissipation of the overall SAM is 4.11 mW given a 20 MHz clock rate