Chua-Chin Wang

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

A CMOS local oscillator using a programmable DLL (delay lock loop)-based frequency multiplier to synthesize carrier frequencies from 1.1 GHz to 1.5 GHz is presented. The frequency of the output clock is 7/spl times/ to 10/spl times/ of an input reference clock. No LC-tank is used in the proposed design, such that the power dissipation as well as the active area are drastically reduced. The design is carried out using the TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the VCDTL (voltage-controlled delay tap line) at the mid point of the working range. Meanwhile, the power dissipation of the physical chip measures only 52.2 mW at 1.2 GHz output.

A boosted wordline voltage generator for low-voltage memories

A novel voltage tripler using 4 clocks with different phases is present in this work. Both the positive and negative polarities of the voltage are generated to serve as the boosted voltage and the back bias voltage. The proposed design is carried out by pass transistors and switched capacitors. The largest generated voltages which the proposed design can provide is +11.09 V and -10.62 V given VDD=3.3 V when the circuit is implemented by TSMC 0.35 /spl mu/m 1P4M CMOS technology.

Bus Guardian Design for automobile networking ecu nodes compliant with FlexRay standards

This paper presents a bus guardian design used in an in-car network compliant with FlexRay standards. FlexRay is a new standard for data/signal communication among electronic devices installed in a vehicle. An 8051-compatible microcontroller was used to implement the system controller. Most important of all is that the bus guardian (BG) in charge of security and safty is proposed and implemented. This work was implemented by hardware description language (HDL) and verified by Xilinx field-programmable gate array (FPGA).

A 4-Kb 667-MHz CMOS SRAM using dynamic threshold voltage wordline transistors

The design of a prototypical 667 MHz CMOS 6-T SRAM is presented. A TSMC (Taiwan Semiconductor Manufacturing Company) 1P6M 0.18 /spl mu/m CMOS process, with 1.8 V power supply, is employed to carry out the entire design. By taking advantage of the large current provided by low V/sub TH/ and low leakage provided by the high V/sub TH/, the threshold voltage of the wordline controlled NMOS transistors of memory cells are variable. When the cell is in the read or write mode, the V/sub TH/ of the wordline controlled NMOS transistors is pulled high such that the drain current is increased. By contrast, if it is idle in a standby mode, their bulk voltage is reduced by shorting their bulk to ground voltage. The proposed 4 Kb 6-T SRAM, by simulated measurement, is found to possess a 2.2 ns access time in the R/W mode, and consume 43.6 mW in the standby mode. The highest operating clock rate is 667 MHz.

A comparison of two alternative architectures of digital ratioed compressor design for inner product processing

Inner product calculations are often required in digital neural computing. The critical path of the inner product of two binary vectors is the carry propagation delay generated from individual product terms. In this work, two novel architectures to arrange digital ratioed compressors are proposed to reduce the carry propagation delay in the critical path. Besides, the carry propagation delay estimation of these compressor building blocks is derived and compared. The theoretical analysis and Verilog simulation both indicate that one of the compressor building blocks we present here might offer a sub-optimal solution for the basic building blocks used in digital hardware realization of the inner product computation.

Dual-polarity high voltage generator design for non-volatile memories

A novel voltage generator using 4 clocks with two different phases is presented in this work to provide a high voltage supply required by non-volatile memories during programming mode and erase mode operations. Both the positive and negative polarities of the voltage are generated to serve as the programming voltage and the erase voltage, respectively. The proposed design is carried out by gated pass transistors and switched capacitors. The regulated generated voltages which the proposed design can provide is +11.7 V and -11.6 V given VDD = 2.5 V when the circuit is implemented by TSMC 0.25 /spl mu/m 1P5M CMOS technology. The maximum power dissipation is estimated to be 3.8 mW given 12.5 MHz clocks.

Mixed-voltage I/O buffer using 0.35 μm CMOS technology

A 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage-tolerant I/O buffer carried out using CMOS 2P4M 0.35 mum process is proposed in this paper. By using a Dynamic gate bias generator to provide appropriate gate voltages for the output stage composed of stacked PMOS and stacked NMOS, the I/O buffer can transmit the signal with higher voltage level (VDDH). Besides, a new floating N-well circuit is proposed to remove the body effect at the output PMOS. Moreover, a Dynamic driving detector is used to balance the turn-on voltages for the PMOS and NMOS in the output stage. The duty cycle of the output signal of the proposed I/O buffer can then be equalized for VDDIO biased at low voltage. The maximum output speed of the proposed design is simulated to be 110/125/110/80/50/20 MHz for VDDIO = 5.0/3.3/2.5/1.8/1.2/0.9 V, respectively. The static power consumption is merely 553 nW in the worst simulation case of [SS, 100degC].

Switched-current 3-bit CMOS wideband random signal generator

The paper presents a switched-current circuit implementation of a chaotic algorithm to generate a white noise. A 3-bit digital normalizer is utilized to adjust the coefficients in the piecewise-linear transfer function such that the probability of the generated numbers will be very close to a uniform distribution. A 1.0 GHz linear sample track-and-hold circuit is applied in the random number generator (RNG) to achieve the goal of a wide 4.0 MHz bandwidth. TSMC 0.25 /spl mu/m 1P5M CMOS process is used to carry out the proposed design. The operating clock is 10 MHz, while the measured bandwidth of the generated noise is 4 MHz.

A ROM-less direct digital frequency synthesizer by using trigonometric quadruple angle formula

A ROM-less direct digital frequency synthesizer (DDFS) employing a trigonometric quadruple angle formula is presented. The spectral purity is better than -130 dBc worst case spur. The resolution is up to 13 bits. Neither any scaling table nor error correction table is required. The maximum error is mathematically analyzed. The word length of each multiplier is carefully selected in the digital implementation such that the error range is limited and the resolution is preserved.

A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation

This paper presents a novel architecture for direct digital frequency synthesizer (DDFS) based on a modified parabolic polynomial interpolation method. A 16-segment parabolic polynomial interpolation is adopted to replace conventional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less fashion such that the speed can be significantly improved. The proposed DDFS is implemented in a standard 0.13 mum cell-based technology. The maximum clock rate is 227 MHz, and the core area is 0.25 mm2. The simulation result shows that the spurious free dynamic range (SFDR) is 117 dBc.