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Dive into the research topics where Chia-Lung Liu is active.

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Featured researches published by Chia-Lung Liu.


international conference on genetic and evolutionary computing | 2010

Efficiency Analysis and Improvement of SIP-based Push-to-Talk over Cellular

Ding-Jyh Tsaur; Chia-Lung Liu

“Push-to-talk over Cellular” (PoC) which is wireless technology and is used on mobile telecom network can enable cell phones capability of one-to-many communications, as the walkie-talkie. PoC is a new potential communication service using cellular network without the defect of walkie-talkie limited communication distance. In this paper, the performance of today’s PoC is evaluated, and the results show that senders may not be able to start talking until about six seconds after pushing the talk key. A long waiting time for users will negatively affect the use of PoC. Therefore, a performance improving scheme is presented in our work to reduce waiting time and number of messages for PoC users.


international conference on communications | 2005

Performance analysis of the sliding-window parallel packet switch

Chia-Lung Liu; Woei Lin; Chin-Chi Wu

The paper is concerned with performance analysis of the parallel packet switch (PPS) with sliding window (SW) scheme. The PPS is composed of multiple packet switches operating independently and in parallel. The traditional PPS dispatch algorithm uses round-robin (RR) (Iyer, S., IEEE Trans. Networking, vol.11, no.2, p.314-24, 2003; Aslam, A. and Christensen, K., LCN 2002, p.270-7, 2002). The class of PPS is characterized by the deployment of parallel center-stage switches such that all memory buffers run slower than the external line rate. We propose a new SW packet switching scheme for the PPS, called SW-PPS. The SW-PPS can operate in a pipeline fashion to achieve the overall switching operation. Under Bernoulli data traffic, the SW-PPS provides significantly higher performance when compared with RR-PPS. The paper presents a mathematical analytical model for RR-PPS and SW-PPS.


advanced information networking and applications | 2005

Evaluation and analysis of the sliding-window parallel packet switch

Chia-Lung Liu; Woei Lin; Chin-Chi Wu

This work analyzes the performance of the parallel packet switch (PPS) with a sliding window (SW) method under bursty data traffic. The PPS comprises multiple packet switches operating independently and in parallel. The typical PPS dispatch algorithm uses a round-robin method (RR) (Iyer, 2003). The class of PPS is characterized by deployment of parallel center-stage switches that all memory buffers run slower than the external line rate. A novel SW packet switching method for PPS, called SW-PPS, is proposed. Under identical bursty data traffic, the SW-PPS provided improved performance when compared to RR-PPS. A mathematical, analytical model for SW-PPS is proposed. In addition, a novel bursty data traffic model is proposed: a packet-based bursty data traffic model. This packet-based bursty data traffic model can emulate more realistic network, and thus, produces more realistic simulation results.


Journal of The Chinese Institute of Engineers | 2007

Performance modeling and analysis of parallel packet switches with piao queues

Chia-Lung Liu; Ding-Jyh Tsaur; Chin-Chi Wu; Woei Lin

Abstract When buffer resources are deployed in the switch, shared‐memory based packet switches are known to supply the best possible performance for bursty data traffic in networks and the Internet. Nevertheless, scaling of shared‐memory packet switches to larger sizes has been limited and then packets can not be processed in a high speed network, chiefly because of the physical restrictions imposed by the memory operation rate and the centralized strategy for switching functions in shared‐memory switches. In this investigation, a scalable switch for a high speed network, which is called the parallel packet switch (PPS), is studied to overcome these constraints. The PPS comprises multiple packet switches operating independently and in parallel. The PPS class is characterized by the deployment of parallel center‐stage switches with memory buffers running slower than the external line rate. Each lower speed packet switch operates at a fraction of the external line rate R. For example, each packet switch can operate at an internal line rate R/K, where K is the number of center‐stage switches. This study develops and investigates a PPS which distributes cells or variable‐length packets to low‐speed switches and uses outputs with push‐in arbitrary‐out (PIAO) queues. We present a novel Markov chain model that successfully analyzes and exhibits PPS performance characteristics for throughput, cell delay and cell drop rate. Simulation comparison demonstrates that the developed Markov chain model is accurate for practical network loads and the PPS with PIAO queues provides considerably better performance than previously known classes of shared‐memory switch architecture.


Journal of Information Science and Engineering | 2007

Speedup Requirements for Output Queuing Emulation with a Parallel Packet Switch

Chia-Lung Liu; Chin-Chi Wu; Woei Lin

This work analyzes whether a parallel packet switch (PPS) can emulate an output-queued (OQ) packet switch. The class of PPS is characterized by the deployment of parallel low-speed switches. Each lower speed packet switch operates at only a fraction of the input line rate R. This study develops and investigates a PPS which distributes cells to low-speed switches and uses outputs with push-in arbitrary-out (PIAO) queues. We present a novel Markov chain model that successfully exhibits these performance characteristics. The simulation results demonstrate that the developed Markov chain model is accurate for practical network loads. The major findings, obtained using the proposed model, are that: (1) the throughput and cell drop rates of a PPS can theoretically emulate those of an OQ packet switch as indicated in Eq. (49); and (2) the cell delay of a PPS can theoretically emulate that of an OQ packet switch as given by Eq. (51).


Journal of Communications and Networks | 2007

Mathematical analysis of the parallel packet switch with a sliding window scheme

Chia-Lung Liu; Chin-Chi Wu; Woei Lin

This work analyzes the performance of the parallel packet switch (PPS) with a sliding window (SW) method. The PPS involves numerous packet switches that operate independently and in parallel. The conventional PPS dispatch algorithm adopts a round robin (RR) method. The class of PPS is characterized by deployment of parallel low-speed switches whose all memory buffers run more slowly than the external line rate. In this work, a novel SW packet switching method for PPS, called SW-PPS, is proposed. The SW-PPS employs memory space more effectively than the existing PPS using RR algorithm. Under identical Bernoulli and bursty data traffic, the SW-PPS provided significantly improved performance when compared to PPS with RR method. Moreover, this investigation presents a novel mathematical analytical model to evaluate the performance of the PPS using RR and SW method. Under various operating conditions, our pro- posed model and analysis successfully exhibit these performance characteristics including throughput, cell delay, and cell drop rate.


international conference on information networking | 2006

A study of matching output queueing with a 3D-VOQ switch

Ding-Jyh Tsaur; Hsuan-Kuei Cheng; Chia-Lung Liu; Woei Lin

In this paper, a novel architecture of three-Dimensional Virtual Output Queue (3D-VOQ) switch is proposed The 3D-VOQ switch requires no speedup and provides an exact emulation of an output-queued switch with a broad class of service scheduling algorithms regardless of its incoming traffic pattern and switch size First, an N×N 3D-VOQ switch was proposed In this architecture, input queues were designed with a few virtual output queues (VOQ) to avoid Head-Of-Line problems and output sides were arranged using sufficient separate queues The combination of this scheme makes switch an input/output contention-free architecture Next, we propose a Small Time- to-leave Cell First (STCF) algorithm of which it can produce a stable many-to-many assignment It is also demonstrated and illustrated that the proposed 3D-VOQ switch can be used to mimic an exact OQ switch Finally, analysis and simulation are employed to verify the performance of 3D-VOQ.


international conference on computational science and its applications | 2006

Performance evaluation of the parallel packet switch with a sliding window scheme

Chia-Lung Liu; Chiou Moh; Chin-Chi Wu; Woei Lin

This study analyzes how parallel packet switching (PPS) performs with a sliding window (SW). The PPS involves numerous packet switches that operate independently and in parallel. The typical PPS dispatch algorithm applies a round-robin method (RR). The class of PPS is characterized by deploying parallel center-stage switches that enable all memory buffers run more slowly than the external line rate. A novel SW packet switching method for PPS, called SW-PPS, is developed. The SW-PPS operates in a pipeline fashion to ensure overall switching. The performance of the RR-PPS and SW-PPS is evaluated for a torus topology. Under identical Bernoulli, the SW-PPS provided considerably outperformed RR-PPS. Furthermore, this investigation proposes a mathematical analytical model for RR-PPS and SW-PPS.


international conference on computational science | 2006

Speedup requirements for output queuing emulation with a sliding-window parallel packet switch

Chia-Lung Liu; Woei Lin; Chin-Chi Wu

This investigation uses an approximate Markov chain to determine whether a sliding window (SW) parallel packet switch (PPS), only operating more slowly than the external line speed, can emulate a first-come first-served (FCFS) output-queued (OQ) packet switch. A new SW packet switching scheme for PPS, which is called SW-PPS, was presented in the authors’ earlier study [1]. The PPS class is characterized by deployment of distributed center-stage switch planes with memory buffers that run slower than the external line speed. Given identical Bernoulli and Bursty data traffic, the proposed SW-PPS provided substantially outperformed typical PPS, in which the dispatch algorithm applies a round-robin method (RR) [1]. This study develops a presented Markov chain model that successfully exhibits throughput, cell delay and cell drop rate. A simulation reveals that the chains are accurate for reasonable network loads. Major findings concerning the presented model are that: (1) the throughput and cell drop rates of a SW-PPS can theoretically emulate those of aFCFS-OQ packet switch when each slower packet switch operates at a rate of around R/K (Eq. 19); and, (2) this investigation also proves the theoretical possibility that the cell delay of a SW-PPS can emulate that of an FCFS-OQ packet switch, when each slower packet switch operates at a rate of about (R/cell delay of FCFS-OQ switch) (Eq. 20).


Archive | 2006

Scheduling Algorithm and Evaluating Performance of a Novel 3D-VOQ switch

Ding-Jyh Tsaur; Hsuan-Kuei Cheng; Chia-Lung Liu; Woei Lin

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Woei Lin

National Chung Hsing University

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Chin-Chi Wu

National Chung Hsing University

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Ding-Jyh Tsaur

National Chung Hsing University

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Hsuan-Kuei Cheng

National Chung Hsing University

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