Chin-Chi Wu

High-performance packet scheduling to provide relative delay differentiation in future high-speed networks

Due to significant advances in interconnection networks and optical technologies, line rate for future high-speed networks can upgrade to terabits per second (Tb/s). Reduction of computational overhead and decrease of packet queueing delay are two critical issues in the design of a packet scheduler for efficiently delivering relative differentiated services over such high-speed networks. In this paper, we propose a new packet scheduler called multi-level dynamic deficit round-robin (MLDDRR). MLDDRR considers packet size and priority at the same time in making scheduling decision. Thus, MLDDRR can deliver relatively small delays not only for traffic of high priority but also for short packets of each class. Because MLDDRR acts like the shortest job first scheduler, MLDDRR can reduce average queueing delay for each class and also provide a better service for real-time applications with a large amount of short packets. MLDDRR also exploits concurrency and pipelining approach to speedup scheduling decision. Furthermore, MLDDRR can protect the traffic of the highest priority from serious performance degradation due to bursts of low priority traffic or high link utilization, and simultaneously prevent the traffic of the lowest priority from starvation. MLDDRR allows network operators to simply change the level of delay differentiation by adjusting parameters. Complexity analysis and extensive simulation results are presented and illustrate that MLDDRR is a high-performance packet scheduler and suitable for being deployed in future high-speed networks to provide relative delay differentiated service.

Improving Inter-server Fairness in Active Queue Management

More than than fifty new active queue management (AQM) algorithms have been proposed since 1999. However, none of them address the inter-server fairness problem. This letter describes the inter-server fairness problem in conventional AQM, and presents a group-based virtual queue algorithm, called GVQ, as a novel AQM approach to solve this problem. The queue complexity and performance of GVQ are evaluated by analysis. The validity of the analytical result and the effectiveness of GVQ are confirmed through ns-2 simulations.

Efficient and fair multi-level packet scheduling for differentiated services

As the demands on quality of service (QoS) of real-time applications over the Internet increase, many research efforts have developed various packet scheduling schemes to support differentiated services. In this paper, we propose a new multi-level packet scheduling algorithm, MLDDRR, enhanced from the existing dynamic deficit round-robin (DDRR) for the support of delay-sensitive applications. The network operator can simply change the level of service differentiation by adjusting parameters. The MLDDRR can achieve high throughput efficiently and simultaneously provide smaller delay for short packets of each service class. The feature of small delay for short packets is of great importance for improving the playback quality of real-time applications such as VoIP or scalable media stream delivery. Simulation results showing the high effectiveness and small overhead of MLDDRR are also presented.

Performance analysis of the sliding-window parallel packet switch

The paper is concerned with performance analysis of the parallel packet switch (PPS) with sliding window (SW) scheme. The PPS is composed of multiple packet switches operating independently and in parallel. The traditional PPS dispatch algorithm uses round-robin (RR) (Iyer, S., IEEE Trans. Networking, vol.11, no.2, p.314-24, 2003; Aslam, A. and Christensen, K., LCN 2002, p.270-7, 2002). The class of PPS is characterized by the deployment of parallel center-stage switches such that all memory buffers run slower than the external line rate. We propose a new SW packet switching scheme for the PPS, called SW-PPS. The SW-PPS can operate in a pipeline fashion to achieve the overall switching operation. Under Bernoulli data traffic, the SW-PPS provides significantly higher performance when compared with RR-PPS. The paper presents a mathematical analytical model for RR-PPS and SW-PPS.

Evaluation and analysis of the sliding-window parallel packet switch

This work analyzes the performance of the parallel packet switch (PPS) with a sliding window (SW) method under bursty data traffic. The PPS comprises multiple packet switches operating independently and in parallel. The typical PPS dispatch algorithm uses a round-robin method (RR) (Iyer, 2003). The class of PPS is characterized by deployment of parallel center-stage switches that all memory buffers run slower than the external line rate. A novel SW packet switching method for PPS, called SW-PPS, is proposed. Under identical bursty data traffic, the SW-PPS provided improved performance when compared to RR-PPS. A mathematical, analytical model for SW-PPS is proposed. In addition, a novel bursty data traffic model is proposed: a packet-based bursty data traffic model. This packet-based bursty data traffic model can emulate more realistic network, and thus, produces more realistic simulation results.

3D-VOQ switch design and evaluation

Input buffered switches with virtual output queues (VOQ) design to avoid head-of-line problems, is a primary design of switches that can be scalable to very high speeds. However, this design requires a complex and iterative scheduling approach and does not meet quality of service (QoS) requirements during operation. In this paper, a three-dimensional virtual output queue (3D-VOQ) switch is proposed and a scheduling algorithm under new architecture that improves the competitive transfer of service. Analysis and simulation are employed to verify the performance of 3D-VOQ, and supports high/low QoS requirements, and then improves switch performance.

Delivering relative differentiated services in future high-speed networks using hierarchical dynamic deficit round robin

With the increasing deployment of real-time audio/video services over the Internet, provision of quality of service (QoS) has attracted much attention. When the line rate of future networks upgrades to multi-terabits per second, if routers/switches intend to deliver differentiated services through packet scheduling, the reduction of computational overhead and elimination of bottleneck resulting from memory latency will both become important factors. In addition, the decrease of average queueing delay and provision of small delays for short packets are two further critical factors influencing the delivery of better QoS for real-time applications. The advanced waiting time priority (AWTP) is a timestamp-based packet scheduler which is enhanced from the well-known WTP. Although AWTP considers the effect of packet size, the latency resulting from timestamp access and a great quantity of computational overhead may result in bottlenecks for AWTP being deployed over high-speed links. Many existing schedulers have the same problems. We propose a multi-level hierarchical dynamic deficit round-robin (MLHDDRR) scheduling scheme which is enhanced from the existing dynamic deficit round-robin scheduler. The new scheme can resolve these issues and efficiently provide relative differentiated services under a variety of load conditions. Besides, MLHDDRR can also protect the highest priority traffic from significant performance degradation due to bursts of low-priority traffic. We compare the performance of AWTP with the proposed scheme. Extensive simulation results and complexity analysis are presented to illustrate the effectiveness and efficiency of MLHDDRR.

Performance modeling and analysis of parallel packet switches with piao queues

Abstract When buffer resources are deployed in the switch, shared‐memory based packet switches are known to supply the best possible performance for bursty data traffic in networks and the Internet. Nevertheless, scaling of shared‐memory packet switches to larger sizes has been limited and then packets can not be processed in a high speed network, chiefly because of the physical restrictions imposed by the memory operation rate and the centralized strategy for switching functions in shared‐memory switches. In this investigation, a scalable switch for a high speed network, which is called the parallel packet switch (PPS), is studied to overcome these constraints. The PPS comprises multiple packet switches operating independently and in parallel. The PPS class is characterized by the deployment of parallel center‐stage switches with memory buffers running slower than the external line rate. Each lower speed packet switch operates at a fraction of the external line rate R. For example, each packet switch can operate at an internal line rate R/K, where K is the number of center‐stage switches. This study develops and investigates a PPS which distributes cells or variable‐length packets to low‐speed switches and uses outputs with push‐in arbitrary‐out (PIAO) queues. We present a novel Markov chain model that successfully analyzes and exhibits PPS performance characteristics for throughput, cell delay and cell drop rate. Simulation comparison demonstrates that the developed Markov chain model is accurate for practical network loads and the PPS with PIAO queues provides considerably better performance than previously known classes of shared‐memory switch architecture.

A Hierarchical Packet Scheduler for Differentiated Services in High-Speed Networks

In this paper, we propose a multi-level hierarchical dynamic deficit round-robin (MLHDDRR) scheduling algorithm enhanced from the existing dynamic deficit round-robin (DDRR) for the support of differentiated services. The level of service differentiation can be changed simply by adjusting parameters. The MLHDDRR scheduler can deliver small delays for short packets of each class. This feature can achieve great delay improvement in comparison with the waiting time priority (WTP) scheduler and is of great importance for improving the QoS of some real-time applications. Moreover, the MLHDDRR scheduler can efficiently provide much better QoS for real-time applications under high link utilizations (95%-99%). Because MLHDDRR is enhanced from DDRR, it is intended to be implemented in high-speed switch systems to deliver short delay and high throughput for the increasing volume of real-time video and audio communication. Extensive simulation results are presented to show the effectiveness of the MLHDDRR scheduler

ERP-DDRR: an efficient and robust scheduler for providing proportional delay differentiation in terabit networks

In recent years, many research efforts focus on relative differentiated service due to the increasing requirements on quality of service for time-sensitive applications. Most of the prior research relies on time stamping arriving packets or periodically monitoring the arrival traffic to arrange the service rate or priority for each class of packets. In this paper, we propose a new efficient and robust packet scheduling scheme, called ERP-DDRR. The ERP-DDRR scheduler not only can provide proportional delay differentiation under various traffic load conditions with very small overhead but also can be implemented in terabit networks. In addition, we propose a pipelining approach to further improve the performance of the ERP-DDRR scheduler. Simulation results show that the ERP-DDRR scheduler provides excellent short-term and long-term performance. The ERP-DDRR scheduler is an excellent alternative solution for future high-speed networks