Chia-Min Chen

Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application

This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35- μm CMOS technology. The device consumes only 25 μA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.

A fast self-reacting capacitor-less low-dropout regulator

A fast self-reacting (FSR) low-dropout (LDO) regulator with triple transient improved loops was implemented in 0.35μm CMOS technology. The proposed regulator for SoC application can achieve high stability for load current from zero to 100mA. The FSR loops can accelerate load transient responses while the regulator achieves the FOM of only 0.00675 (ps) without an output capacitor. The experimental results show the load regulation of 75.2 μV/mA and line regulation of 1.046 mV/V. The whole LDO chip consumes a quiescent current of 27 μA with an ultra low dropout voltage of 142mV at the maximum output current of 100mA. The proposed FSR transient improved loops can effectively reduce the transient voltage undershoot and overshoot. While the load current switches between 0 and 100 mA with both rise and fall time of 1 μs, the result shows that the maximum undershoot is 25 mV and that the maximum overshoot is 5 mV. When the full load current is 100mA, the undershoot and the overshoot of the line transient response are 4 mV and 6.5 mV, respectively, for a 1 V step supply waveform with 5 μs transient time.

A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation

A low power CMOS voltage reference circuit was designed and implemented by TSMC 0.18-mum CMOS process. The voltage reference circuit uses the VGS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining the weighted VGS difference with weak-inversion VGS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/degC in [-20degC~120degC] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm2 and dissipates 17.25 muW at room temperature. By connecting a 0.22 muF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 muV/radicHz and 22.2 muV/radicHz, respectively.

A capacitor-free CMOS low-dropout voltage regulator

This paper presents novel frequency compensation techniques for low-dropout (LDO) voltage regulator. An enhanced active feedback frequency compensation is employed to improve its frequency response. This LDO can provide high stability for loading current range up to 100 mA without loading capacitors. Moreover, the total compensation capacitors only require 7 pF for this technique. This allows us to integrate the compensation capacitors within the LDO chip easily. The proposed LDO regulator was designed using TSMC 0.35-µm CMOS technology. With an active area of 0.14 mm2, the quiescent current is only 40 µA. The input voltage is ranged from 1.73 V to 5 V for loading current of 100 mA and the output voltage of 1.5 V. The main advantage of this approach is that the LDO circuit can be stable when we connect external load capacitors with ultra low ESR, or even when we eliminate the load capacitors.

Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump

This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. The loop bandwidth of the system can be adjusted by the control voltage so as to reduce the locking time. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of -114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below -74 dBc.

An inductor-coupling resonated CMOS low noise amplifier for 3.1–10.6GHz ultra-wideband system

In this paper, a low power low-noise amplifier (LNA) using inductor-coupling resonated technique is designed for ultra-wideband (UWB) wireless system. The design consists of a wideband input impedance matching network, one stage cascode amplifier with inductor-coupling resonated load, and an output buffer; it was fabricated in TSMC 0.18um standard RF CMOS process. The UWB LNA gives 10.8dB power gain and 9.4GHz 3dB bandwidth (1.2GHz – 10.6GHz) while consuming only 6.2mW through a 1.2V supply, including output buffer. Over the 3.1GHz – 10.6GHz frequency band, a minimum noise figure of 3.9dB and input return loss lower than −5.7dB have been achieved.

A fourth-order feedforward continuous-time delta-sigma ADC with 3MHz bandwidth

A fourth-order feedforward continuous-time (CT) delta-sigma modulator is presented. The modulator takes an active-RC OpAmp as the first stage because of the high-linearity requirement, and the other three stages are composed by Gm-C integrators. In feedforward topology, a higher out-of-band NTF gain could be taken for better performance. As we know, the most important part in the feedforward CT ΔΣ modulator is the summation circuit for the feedforward paths. The modulator uses a tuning adder, which we propose, to make sure the modulator can work correctly even under the influence of the process variation on resistors. Finally, the delta-sigma modulator is implemented in standard digital 0.18-µm CMOS process, which achieves 57.84 dB SNDR over a 3MHz signal bandwidth at an OSR of 16.67. The power consumption of the CT delta-sigma modulator is 11.8 mW from the 1.8-V supply.

A high efficiency current-mode DC-DC step-down converter with wide range of output current

This paper presents a high efficiency current-mode DC-DC step-down converter with wide range of output current. The converter adaptively operates as Pulse-Width Modulation (PWM). An on-chip current sensing technique is employed to reduce external components and no extra I/O pins are needed for the current-mode controller. A soft-start operation is designed to eliminate the excess large current during the startup of the regulator. The circuit has been designed with TSMC 2P4M 0.35 µm CMOS process. The range of the supply voltage is from 2 to 5V, which is suitable for single-cell lithium-ion battery.

A single-inductor multiple-output boost converter with freewheel charge-pump control

This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC-DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies only 1.3×1.3 mm2. Experimental results demonstrate that the converter successfully generates four wellregulated outputs with a single inductor. The supply voltage ranged from 1.6 V to 2.5 V and the load regulation performance was 0.08 mV/mA, 0.05mV/mA, 1.7 mV/mA, and 1.9 mV/mA for VO1, VO2, VO3 and VO4, respectively.

Dual-output switched-capacitor DC-DC converter with peseudo-three-phase swap-and-cross control and amplitude modulation mechanism

This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The two outputs were regulated at 2.5 V and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz. The maximal peak-to-peak output ripple voltages for the two outputs under 100 mA load currents were suppressed to below 26 mV and 20 mV, respectively.