Chung-Chih Hung

A low-voltage, low-power CMOS fifth-order elliptic GM-C filter for baseband mobile, wireless communication

The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication are presented. The operational transconductance amplifier (OTA) used in this filter is a low-voltage rail-to-rail voltage-to-current converter (V-I converter). In this V-I converter, an N-type V-I converter cell is connected in parallel with its counterpart, a P-type V-I converter cell, to achieve common-mode (CM) rail-to-rail operation. Two maximum-current selecting circuits and an output current subtraction circuit are utilized to generate constant-g/sub m/ output currents for this OTA. This fifth-order elliptic low-pass GM-C filter operates at a supply voltage of 3 V and has a cutoff frequency of 280 to 405 kHz. It provides up to 700 mV/sub pp/ output with 1% total harmonic distortion (THD), dissipates 2.48 mW at V/sub cm/=1.5 V, and occupies 1.62 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.

A Wide Tuning Range G

A third-order channel selection filter for multi-mode direct-conversion receivers is presented. The filter is designed with a Butterworth prototype and with the target wireless applications of Bluetooth, cdma2000, wideband CDMA, and IEEE 802.11a/b/g/n wireless LANs. Linear-region MOS transistors are used to perform voltage-to-current conversion. The wide tuning range is achieved by the current multipliers and linear voltage-to-current converters. Implemented in the TSMC 0.18 mum CMOS process, the measurement results show that the filter can operate successfully over a cutoff frequency range of 500 kHz to 20 MHz, and is compliant with the requirements of different wireless applications. The power consumption is 4.1 mW to 11.1 mW for minimum and maximum cutoff frequencies respectively from a 1.2 V supply voltage. The circuit performance compares favorably with previously reported works.

_{\rm m}

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims.

–C Filter for Multi-Mode CMOS Direct-Conversion Wireless Receivers

A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused b y common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about third-order inter-modulation (IM3) distortion for up to 0.9 at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1 x 10-3 mm2 and the power consumption is 9.5 mW under a 1.5-V supply voltage.

High performance analog VLSI computational circuits

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm2

A 40-MHz Double Differential-Pair CMOS OTA With

This paper presents CMOS low-voltage rail to-rail voltage-to-current (V-I) converters which could be used as basic building blocks to construct low-voltage current-mode analog very large scale integration (VLSI) circuits. In the circuit, an n-type V-I converter cell is connected in parallel with its p-type counterpart to achieve common-mode rail to-rail operation. A linear differential relationship of the n-type V-I converter, or its p-type complement, is obtained using a new class-AB linearization technique. The constant transconductance value is obtained by manipulating the DC bias currents of n- and p-type V-I converter cells. The circuit can operate from rail to rail with a power supply of 3 V or less, depending on the VLSI technology and the DC bias current level.

-{\hbox{60-dB}}

A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A/sub 0/=70 dB, GBW=5.5 MHz, SR=7 V//spl mu/s, and /spl upsi//sub n/=10nV//spl radic/Hz@100 kHz. With a supply voltage of /spl plusmn/5 V, the amplifier has a /spl plusmn/4.7 V output swing and features a low 30 /spl Omega/ open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V/sub out,pp/ output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.

IM3

A third-order channel selection filter for multi-mode direct-conversion receiver is presented. The filter is designed based on the Butterworth prototype with the target applications of bluetooth, cdma2000, wideband CDMA, and IEEE 802.11 a/b/g/n wireless LANs. Linear region MOS transistors are used to perform the voltage-to-current conversion. The wide tuning range can be achieved by the translinear loop followed by the linear voltage-to-current converter. Implemented in the TSMC 0.18-mum CMOS process, the measurement results show that the filter can operate with the cutoff frequency of 500 kHz to 20 MHz, and thus meet the requirement of different wireless applications. In the design, the maximum power consumption is 11.1 mW under a 1.2-V supply voltage. The figure of merit (FOM) is favorably compared with the other previously reported works.

A Wide Tuning Range

This paper introduces a low-voltage rail-to-rail wide range CMOS Differential Difference Amplifier (DDA). The input stage of this DDA comprises two rail-to-rail VI converters with large signal handling capability. In each V-I converter, an N-type converter cell is connected in parallel with its P-type counterpart cell in order to cover all the operating range of the common-mode input voltage. Its constant transconductance is achieved through the use of two maximum-current selecting circuits and an output substraction stage. Simulation results of the DDA with 3 V supply show that the DDA has a rail-to-rail constant input transconductance, a rail-to-rail output swing, 66 dB open-loop gain, and a 2.2 MHz bandwidth with C/sub L/=30 pF and R/sub L/=250 /spl Omega/. Low-voltage DDA-based circuits, such as an adder/substractor and an integrator, are given in this paper. They constitute basic blocks of modern low-voltage analog signal and information processing systems.

G_{m}

This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35- μm CMOS technology. The device consumes only 25 μA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.