Chia Yee Ooi

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

Low latency network-on-chip router microarchitecture using request masking technique

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%-20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

A New Class of Sequential Circuits with Acyclic Test Generation Complexity

This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation procedure for acyclically testable sequential circuits and elaborate a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuit. Since the class of acyclically testable sequential circuits is larger than the class of acyclic sequential circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.

Low latency network-on-chip router using static straight allocator

One clock cycle is the ideal latency for a network-on-chip (NoC) router to pass the received flit in the current cycle to its requested destination output port when there is no contention with other flits. In order to achieve this goal, a newly arrived flit is required to go through all routers pipeline stages to the switch traversal stage. In this paper, we present a low latency synchronized NoC router micro-architecture that achieves single clock cycle latency for packets traveling to the same direction using a static straight VC/SW allocator (SSA). In comparison to existing single clock cycle latency routers which require more complex VC/SW allocator or crossbar switch architectures, our proposed SSA has simpler architecture and works in parallel with the previously proposed baseline VC/SW allocator. The simulation results using six different synthetic traffic patterns shows SSA reduces the communication latency of a 2-cycle latency baseline router by 24% in average.

Feasible transition path generation for EFSM-based system testing

This paper presents a feasible transition path (FTP) generation approach for testing extended finite state machines (EFSM). The major problem faced by EFSM-based testing is the existence of the infeasible paths due to conflict of the context variable with the enable conditions in the transition path. In order to avoid infeasible path generation, this paper proposed an approach that uses the modified breadth first search with conflict checker to generate a set of minimum FTP for each transition. An EFSM executable model is developed for algorithm modeling and verification as well as performance evaluation. Experimental results conducted on two EFSM models showed that the proposed approach is able to generate feasible transition path with at least 18% path length reduction.

A New Scan Design Technique Based on Pre-Synthesis Thru Functions

VLSI design has moved from bottom-up design approach to top-down design methodology with the aid of advanced computer-aided design (CAD) technology. This paper introduces a new scan design technique as a design-for-test (DFT) method for sequential circuits by exploiting the information of thru functions available at high-level description of the circuit. This DFT method reduces the number of flip-flops to be converted into scan flip-flops because some existing thru functions allow the flip-flops to be controllable from primary inputs or observable at primary outputs or both. Moreover, the DFT method can be applied to both structural RT-level circuits and gate-level circuits. The paper also presents a test generation procedure for the augmented sequential circuits using a combinational ATPG tool. The experimental results show the comparison of our DFT method with conventional scan techniques in terms of hardware overhead, test generation time, fault coverage, fault efficiency and test application time

Classification of Sequential Circuits Based on τk Notation and Its Applications

This paper introduces τk notation to be used to assess test generation complexity of classes of sequential circuits. Using τk notation, we reconsider and restate the time complexity of test generation for existing classes of acyclic sequential circuits. We also introduce a new DFT method called feedback shift register (FSR) scan design technique, which is extended from the scan design technique. Therefore, for a given sequential circuit, the corresponding FSR scan designed circuit has always equal or lower area overhead and test application time than the corresponding scan designed circuit. Furthermore, we identify some new classes of sequential circuits that contain some cyclic sequential circuits, which are τ-equivalent and τ2-bounded. These classes are the l-length-bounded testable circuits, l-length-bounded validity-identifiable circuits, t-time-bounded testable circuits and t-time-bounded validity-identifiable circuits. In addition, we provide two examples of circuits belonging to these classes, namely counter-cycle finite state machine realizations and state-shiftable finite state machine realizations. Instead of using a DFT method, a given sequential circuit described at the finite state machine (FSM) level can be synthesized using another test methodology called synthesis for testability (SFT) into a circuit that belongs to one of the easily testable classes of cyclic sequential circuits.

Classification of sequential circuits based on /spl tau//sup k/ notation

In this paper, we introduce a new test generation complexity notation called /spl tau//sup k/ notation, which consists of /spl tau//sup k/-equivalent and /spl tau//sup k/-bounded, in order to clarify the classification of sequential circuits based on combinational test generation complexity. We reconsider the test generation complexity for the existing classes of acyclic sequential circuits. Several new classes of sequential circuits that cover some cyclic sequential circuits have been identified as being /spl tau/-equivalent and /spl tau/-bounded.

rrBox: A remote dynamically reconfigurable network processing middlebox

This paper presents a remote dynamically reconfigurable network processing middlebox. The packet forwarding and other network functional circuitry in the data plane of this middlebox can be updated remotely at run-time by client computer through 1Gbps Ethernet connection. The proposed architecture is stand-alone and uses a customized reconfiguration controller and Internal Configuration Access Port to achieve dynamic reconfiguration. Data plane functional update enables feature extension, customization, optimization and patch on design flaws, which is crucial for application to cope with the changes in operational constraints. A case study on network protection using this platform is included to verify the developed platform and to demonstrate the benefits of remote functional updates. Based on experimental result, the implemented middlebox achieved roughly 350Mbps reconfiguration throughput, which is beneficial in mass remote update with low device downtime for functional update.

Built-in Self Test Power and Test Time Analysis in On-chip Networks

Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of verification, HSPICE simulation and FPGA implementation are used. The switching activities are computed using a special purpose cycle-accurate NoC simulator. At the end, the model is used to calculate test power and spot the most energy consuming and area occupying component of a typical NoC testing circuit.