Nasir Shaikh-Husin

A Particle Swarm Optimization Approach for Routing in VLSI

The performance of very large scale integration (VLSI) circuits is depends on the interconnected routing in the circuits. In VLSI routing, wire sizing, buffer sizing, and buffer insertion are techniques to improve power dissipation, area usage, noise, crosstalk, and time delay. Without considering buffer insertion, the shortest path in routing is assumed having the minimum delay and better performance. However, the interconnect delay can be further improved if buffers are inserted at proper locations along the routing path. Hence, this paper proposes a heuristic technique to simultaneously find the optimal routing path and buffer location for minimal interconnect delay in VLSI based on particle swarm optimization (PSO). PSO is a robust stochastic optimization technique based on the movement and information sharing of swarms. In this study, location of doglegs is employed to model the particles that represent the routing solutions in VLSI. The proposed approach has a good potential in VLSI routing and can be further extended in futureTo seek for a hyperchaotic attractor with complex topological attractor structure, a new four-dimensional continuous autonomous hyperchaotic system is proposed. Within a wider region of the variation of the control parameter, this system can generate novel hperchaotic and chaotic attractors along with quasi-periodic and periodic orbits. By employing Lyapunov exponent spectrum, bifurcation diagram, Poincaré mapping and phase portrait, etc., the existence of hyperchaotic behaviors of new system is verified and the dynamical routes from period, quasi-period, chaos and hyperchaos are observed. Furthermore, a practical circuit is designed to realize the system, which the experimental results indicate that new four-dimensional hyperchaotic system is a realizable chaotic system with potential values of engineering applications.

FPGA implementation of RSA public-key cryptographic coprocessor

The hardware implementation of the RSA algorithm for public-key cryptography is presented. The algorithm is dependent on the computation of modular exponentials. Critical to this computation is a fast implementation of modular multiplications. A high-performance systolic array architecture for modular multiplication based on the algorithm of Montgomery (1985) is proposed. The design is targeted for implementation in reconfigurable logic, which can yield custom-hardware performance yet maintains all the flexibility of software-based systems. Reconfigurable computing allows the designer to respond, in the prototyping stage, to flaws discovered in implementation or to changes in standards or data formats. We report the issues involved in the preliminary design of the prototype to be fabricated in Altera FLEX10KE series FPGA mounted on a PCI card.

Implementation of recurrent neural network algorithm for shortest path calculation in network routing

This paper describes the architecture and implementation of a shortest-path processor, both in reconfigurable hardware and VLSI. This processor is based on the principles of a recurrent spatiotemporal neural network. The processors operation is similar to E.W. Dijkstras (1959) algorithm and it can be used for network routing calculations. The objective of the processor is to find the least-cost path in a weighted graph between a given node and one or more destinations. The digital implementation, which exhibits a regular interconnect structure and uses simple processing elements, is well-suited for VLSI implementation and reconfigurable hardware.

Network partitioning and GA heuristic crossover for NoC application mapping

Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic algorithm approach that incorporates network partitioning and heuristic crossover techniques to improve the NoC application mapping. Our experiment on VOPD (video object plane decoder) shows that our proposed method results in only 0.2% to 0.8% communication cost difference compared to global optimal mapping and 6% better communication cost compared to technique using conventional GA.

Feasible transition path generation for EFSM-based system testing

This paper presents a feasible transition path (FTP) generation approach for testing extended finite state machines (EFSM). The major problem faced by EFSM-based testing is the existence of the infeasible paths due to conflict of the context variable with the enable conditions in the transition path. In order to avoid infeasible path generation, this paper proposed an approach that uses the modified breadth first search with conflict checker to generate a set of minimum FTP for each transition. An EFSM executable model is developed for algorithm modeling and verification as well as performance evaluation. Experimental results conducted on two EFSM models showed that the proposed approach is able to generate feasible transition path with at least 18% path length reduction.

FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application

Moving target detection is the most common task for Unmanned Aerial Vehicle UAV to find and track object of interest from a bird’s eye view in mobile aerial surveillance for civilian applications such as search and rescue operation. The complex detection algorithm can be implemented in a real-time embedded system using Field Programmable Gate Array FPGA. This paper presents the development of real-time moving target detection System-on-Chip SoC using FPGA for deployment on a UAV. The detection algorithm utilizes area-based image registration technique which includes motion estimation and object segmentation processes. The moving target detection system has been prototyped on a low-cost Terasic DE2-115 board mounted with TRDB-D5M camera. The system consists of Nios II processor and stream-oriented dedicated hardware accelerators running at 100 MHz clock rate, achieving 30-frame per second processing speed for 640 × 480 pixels’ resolution greyscale videos.

Hardware acceleration of a face detection system on FPGA

Face detection is a computer technology that has been used in various applications such as biometric authentication, surveillance, computer interaction and social media. It is the process of detecting faces in an image or video stream and is an important step that precedes face recognition. Many researchers in recent years are implementing real time and accurate face detection system on FPGA due to computing resource and design flexibility. This paper presents an implementation of a face detection system accelerated on FPGA for high throughput. The proposed system utilizes stream-oriented hardware architecture to perform image pre-processing, skin segmentation, filtering as well as connected component labeling processes. Window-based image processing such as median and morphological filtering were accelerated using line buffering technique to achieve maximum throughput. The detection system was implemented on an Altera Cyclone IV FPGA and was benchmarked against a software implementation using NIOS II soft-core processor. The hardware design achieved a speed-up of 250 times compared to software implementation when processing a RGB video frame of 800×600 pixel size.

Network partitioning domain knowledge multiobjective application mapping for large-scale network-on-chip

This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC). As the number of intellectual property (IP) cores in multiprocessor system-on-chip (MPSoC) increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA). The initial population of GA is initialized with network partitioning (NP) while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

Pulse coded neural network implementation in VLSI

A neural network that encodes signals in terms of pulses has been designed and fabricated. The neural network components are described in detail. As a test case, a two-layer network is implemented. A preliminary test result shows some promise and some limitations of the design.

Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms

Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, HTM performance is application-specific and determined by version and conflict management configurations. Most previous HTM implementations for embedded system in literature were built on fixed version management that result in significant performance loss when transaction behaviour changes. In this paper, we propose a HTM targeted for embedded applications which is able to adapt its version management based on application behaviour at runtime. It is prototyped and analysed on Altera Cyclone IV platform. Random requests at different contention levels and different transaction sizes are used to verify the performance of the proposed HTM. Based on our experiments, lazy version management is able to obtain up to 12.82% speed-up compared to eager version management at high contention level. Meanwhile, eager version management obtains up to 37.84% speed-up compared to lazy version management at low contention. The adaptive mechanism is able to switch configuration at runtime based on applications behaviour for maximum performance.