Chiaki Kudou

Novel SiC power MOSFET with integrated unipolar internal inverse MOS-channel diode

A novel SiC power MOSFET with an integrated unipolar internal inverse diode has been developed for the first time. Our novel SiC MOSFET has two specific features. One is that the growth of the SiC crystal defects caused by the continuous bipolar forward current of the internal diode with pn junction is completely eliminated because the unipolar diode current passes through the MOS channel region. The other is that the very small-size power modules and/or power systems are successfully designed because the external inverse diode chips paired with the transistor chips are not necessary.

Suppression of 3C-Inclusion Formation during Growth of 4H-SiC Si-Face Homoepitaxial Layers with a 1° Off-Angle

We grew epitaxial layers on 4H-silicon carbide (SiC) Si-face substrates with a 1° off-angle. The suppression of 3C-inclusion formation during growth at a high C/Si ratio was investigated, because a growth technique with a high C/Si ratio is needed to decrease residual nitrogen incorporation. 3C inclusions were generated both at the interface between the substrate and epitaxial layer, and during epitaxial growth. 3C-SiC nucleation is proposed to trigger the formation of 3C inclusions. We suppressed 3C-inclusion formation by performing deep in situ etching and using a high C/Si ratio, which removed substrate surface damage and improved the 4H-SiC stability, respectively. The as-grown epitaxial layers had rough surfaces because of step bunching due to the deep in situ etching, but the rough surface became smooth after chemical mechanical polishing treatment. These techniques allow the growth of epitaxial layers with 1° off-angles for a wide range of doping concentrations.

Homo-Epitaxial Growth on 2° Off-Cut 4H-SiC(0001) Si-Face Substrates Using H2-SiH4-C3H8 CVD System

We have grown epitaxial layers on 2° off-cut 4H-SiC(0001) Si-face substrates. The epitaxial layer surfaces on 2° off-cut substrates are more prone to generate step-bunching than on 4° off-cut substrates, which are observed by confocal microscopy with differential interference contrast. We have speculated that the step-bunching is generated at the beginning of an epitaxial growth. Triangular defect density of epitaxial layers on 2° off-cut substrates is as low as 0.7 cm–2 for the size corresponding to 150 mm. We have firstly reported distribution of 2° off-cut epitaxial layers for the 150-mm size using two 76.2-mm wafers: σ/mean = 3.3% for thickness, σ/mean = 7.3% for carrier concentration.

Starting Point of Step-Bunching Defects on 4H-SiC Si-Face Substrates

On 4H-SiC Si-face substrates after H2 etching, the defect with “line” feature parallel to a step as “bunched-step line” was observed. Using X-ray topography and KOH etching, we confirmed that the bunched-step line originated from basal plane dislocation (BPD). Use of the substrate with the lowest BPD density will be effective to reduce bunched-step line that would affect oxide layer reliability on an epitaxial layer. However, more detail investigation needs to classify the BPD that would become a starting point of bunched-step line.

Influence of Epi-Layer Growth Pits on SiC Device Characteristics

Homoepitaxial layers with different growth pit density were grown on 4H-SiC Si-face substrates by changing C/Si ratio, and the influence of the growth pit density on Schottky barrier diodes and metal-oxide-semiconductor capacitors were investigated. Even though there were many growth pits on the epi-layer, growth pit density did not affect the leakage current of Schottky barrier diodes and lifetime of constant current time dependent dielectric breakdown. By analyzing the growth pit shape, the aspect ratio of the growth pit was considered to be the key factor to the leakage current of the Schottky barrier diodes and the lifetime of metal-oxide-semiconductor capacitors.

Homoepitaxial growth and investigation of stacking faults of 4H-SiC C-face epitaxial layers with a 1° off-angle

We grew epitaxial layers on 4H-SiC C-face substrates with a 1? off-angle, and discussed important factors related to stacking fault (SF) density reduction by investigating the causes of SFs. Three types of SFs were generated, namely 3C inclusions, 8H-SFs and -SFs. The 3C inclusions were caused by 3C-SiC particles, which were present on the substrates before epitaxial growth, or which had fallen onto the substrates during epitaxial growth from the inside walls of a chemical vapor deposition reactor. The 3C-inclusion density decreased when the in-situ H2 etching depth exceeded 0.4 ?m because the 3C-SiC particles, which were present on substrates before epitaxial growth, were removed. For 8H-SFs and -SFs, high dislocation density areas on the substrates rather than the dislocations themselves cause these SFs. To reduce the density of these SFs, it is important to suppress generation of the high dislocation density areas on the substrates.

Uniformity Improvement in Carrier Concentration on 150 mm Diameter C-Face Epitaxial Growth of 4H-SiC

The guidelines necessary to improve the n-type doping uniformity on C-face epitaxial growth of 4H-SiC have been examined as far as the practical throughput is maintained, e.g. 3×150 mm wafers with the growth rate higher than 20 μm/h. The flow-channel enlargement was carried out and the effect was estimated by temperature distribution estimation performed by hydrogen etching. Also, effective C/Si was simulated with the temperature distribution obtained from the hydrogen etching experiments. As a result, positional agreement was found between the region where carrier concentration begins to increase and the drastic drop in temperature and the effective C/Si ratio.

Conversion of Basal Plane Dislocations to Threading Edge Dislocations in Growth of Epitaxial Layers on 4H-SiC Substrates with a Vicinal Off-Angle

We have investigated a conversion of basal plane dislocation (BPD) to threading edge dislocation (TED) in growth of epitaxial layers (epi-layers) on 4H-SiC vicinal substrates with an off-angle of 0.85° at low C/Si ratio of 0.7 by using deep KOH etching and X-ray topography observations. Deep KOH etching indicated that BPDs in the substrates converted to TEDs in the epi-layers. X-ray topography observations suggested that the conversion occurred during epitaxial growth when the thickness of epi-layers was less than 1.5 μm. We found that the conversion ratio obtained from counting deep KOH etch pits was over 99%.

C-Face Epitaxial Growth of 4H-SiC on Quasi-150-mm Diameter Wafers with High Throughput

C-face epitaxial growth of 4H-SiC was investigated considering the use as drift layers of high blocking voltage SiC power MOSFETs, such as 3.3 kV, using a multiple-wafer epitaxy system. As high as 50.9 μm/h was achieved as the growth rate while maintaining specular surface within quasi-150 mm-diameter wafers. Also, it has been found that the background carrier concentration could be lowered enough to control the desired n-type doping concentration of nitrogen. In addition, high-throughput has been confirmed by comparing the current data with the recent results reported.

Improvement of 4H-SiC Epitaxial Layers Grown on 2o Offcut Si-Face Substrates

The surface quality of epitaxial layers grown on 2° offcut substrates was improved. These substrates require a lower growth temperature and a lower C/Si ratio than their 4° offcut counterparts to suppress macro step bunching. Surface morphology, triangular defect density, and doping uniformity presented a trade-off relationship with respect to growth parameters. The implementation of a low C/Si ratio buffer layer led to a balance between surface defect density, which reached a minimum of 0.2 cm−2, and good doping uniformity on an equivalent wafer size (150 mm). An evaluation of metal–oxide–semiconductor capacitors and Schottky barrier diodes fabricated on 2° offcut epitaxial layers showed that the quality of these epitaxial layers was satisfactory for application in devices.