Chiao-Ling Lung

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization

Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. The multi-core processor (MCP), which is able to deliver equivalent performance with less power consumption, is a candidate for 3D implementation. However, when maximizing the throughput of 3D MCP, due to the inherent heat removal limitation, thermal issues must be taken into consideration. Furthermore, since the temperature of a core strongly depends on its location in the 3D MCP, a proper task allocation helps to alleviate any potential thermal problem and improve the throughput. In this paper, we present a thermal-aware on-line task allocation algorithm for 3D MCPs. The results of our experiments show that our proposed method achieves 16.32X runtime speedup, and 23.18% throughput improvement. These are comparable to the exhaustive solutions obtained from optimization modeling software LINGO. On average, our throughput is only 0.85% worse than that of the exhaustive method. In 128 task-to-core allocations, our method takes only 0.932 ms, which is 57.74 times faster than the previous work.

Clock skew optimization considering complicated power modes

To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among modules, whereas the module-level CTO reduces clock skew within a single module. Our experimental results show that the power-mode-aware CTO can achieve significant improvement in the worst-case condition with only a minor penalty in area.

Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization

3-D many-core processor (3-D MCP) has become an emerging technology to tackle the power wall problem due to rapidly increasing number of transistors. However, when maximizing the throughput of 3-D MCP, which is expressed as a weighted sum of the speeds, due to the inherent heat removal limitation, thermal issues must be taken into consideration. Since the temperature of a core strongly depends on its location in the 3-D IC, a proper task allocation can alleviate the thermal problem and improve the throughput. Nevertheless, conventional techniques require computationally intensive thermal simulation, which prohibits its usage from the online application. In this paper, we propose an efficient online task allocation and task migration algorithm attempting to maximize the throughput of 3-D MCP simultaneously, considering unfinished tasks left from the last scheduling interval and new incoming tasks of this scheduling interval. The results of our experiments show that our proposed method achieves a 20.82X runtime speedup. These results are comparable to the exhaustive solutions obtained from optimization-modeling software LINGO. In addition, on average, our throughput results, with and without consideration of unfinished tasks, are only 4.39% and 0.69% worse, respectively, than that of the exhaustive method. In 128 task-to-core allocations, our method takes only 0.951 ms, which is 59.39 times faster than that of the previous work.

Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability

Soft error has become an important reliability issue in advanced technologies. To tolerate soft errors, solutions suggested in previous works incur significant performance and power penalties, especially when a design with fault-tolerant structures is overprotected. In this paper, we present a soft-error-tolerant design methodology to tradeoff performance, power, and reliability for different applications. First, four novel detection and correction flip-flop (FF) structures are proposed to provide different levels of tolerance capability against soft errors. Second, architecture-level vulnerability and logic-level susceptibility analyses are employed to identify weak FFs that can easily cause program execution errors. Third, an optimization framework is developed to synthesize the proposed four novel FF structures into weak and highly observable storage bits with the flexibility of trading off performance, power, and reliability. A five-stage pipeline RISC core (UniRISC) is adopted to demonstrate the usefulness of our methodology. Experimental results show that the proposed method can accomplish design goals by balancing performance, power, and reliability. For example, we can not only satisfy the reliability requirement that no more than five errors occur per one billion hours in a design but also reduce up to 87% performance overhead and 91% power overhead when compared with previous works.

Floorplanning 1024 cores in a 3D-stacked networkon- chip with thermal-aware redistribution

As the performance of a processing system is to be significantly enhanced, on-chip many-core architecture plays an indispensable role. Explorations of a suitable three-dimensional integrated circuit (3D IC) with through-silicon via (TSV) to realize a large number of processing units and highly dense interconnects certainly attract the attention. However, the combination of processors, memories, and/or sensors in a die stack leads to the cooling problem in a tottering situation. Consequently, a thermal solution which has a high heat removing rate seems unavoidable. The floorplan and routing of the chip should be rearranged after the thermal solution is performed. By utilizing the thermal ridge, the routing spaces between hot core-groups (CGs) need to be expanded until they cannot affect each other. Under the constraint of 20% area overhead for the thermal ridges, we place the thermal ridges with different densities of thermal TSVs between the hottest CGs on the chip. For a 1024-core network on chip (NoC) design studied in this paper, the maximum temperature decreases from 408 K to 372 K, and the temperature nonuniformity is improved from 3.8 K/cm to 0.5∼1.5 K/cm. This means that the temperature difference between two neighboring CGs is less than 0.06 K. Compared with micro-fluidic cooling channel, the proposed thermal ridge scheme is much more costeffective and easy to implement.

LP-based multi-mode multi-corner clock skew optimization

Clock skew optimization is a complicated problem in modern VLSI technologies because circuits often operate in many environments (corners) such as different power supply voltage and temperature or functional modes (modes) like voltage modes. While circuits operate in different corners or modes, cell delay varies a lot. It will lead to large skew variation. Therefore, to optimize clock skew in all corners or modes is very important. In this paper, we develop an approach to minimize clock skew considering multi-corner multi-mode conditions. Our experimental results shows there are 10.3% improvement compared with the commercial tool SOC Encounter.

Thermal analysis experiences of a tri-core SoC system

Higher temperature induced by higher power density results in higher cost, lower performance and lower reliability. The thermal effects become important issues of todays VLSI design. In this paper, we adopt a RC-based thermal model to perform the steady-state and transient thermal analysis for a tri-core SoC system. The power information is generated from the ESL power estimation. The results show that the lateral heat dissipation cannot be ignored since hot spots occur in the vicinity where the nearby blocks with high power density, but none of hot spots with the highest power density. Finally, we also compare our fast RC based thermal analysis model with commercial CFD (Computational Fluid Dynamics) software whose runtime is extremely slow. The results show the high degree of consistency.

TSV fault-tolerant mechanisms with application to 3D clock networks

Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. Through Silicon Via (TSV) formation is one of the key enabling technologies for 3D ICs. While TSVs provide vertical connections between different dies for higher performance, they suffer from random open defects and thermo-mechanical stress. The potential yield loss can significantly increase the mass production cost, which in turn affects the profitability of 3D ICs. To address the TSV reliability issues, double TSV, shared spare TSV and TSV fault tolerant unit (TFU) techniques have been developed. In this paper, we briefly review them and use 3D clock networks as a vehicle to compare their effectiveness and overhead.

Thermal stress aware design for stacking IC with through glass via

Stacking die technology using interposer with through-substrate-via technology has attracted a lot of attention due to various advantages in performance and integration. Interposers with through-glass-vias (TGVs) are widely studied due to their excellent electrical properties. However, a high temperature environment during the fabrication process of TGV leads to uncontrollable thermal expansion, which then causes a serious reliability problem. In this paper, we present an efficient algorithm to place micro bumps to reduce stress surrounding TGVs in appropriate positions that can minimize the total number of micro bumps needed. Our simulated results show that significant reduction on the maximum stress can be achieved. Not only the proposed design can lower the maximum temperature of the hotspot, but improve the thermal uniformity of the test chip.

Design and implementation of 3D-thermal test chip for exploration of package effects

Thermal solution and thermal management are critical issues in either 2.5D or 3D stacking design, especially when the hotspots are not located next to the heat sink. On the other hand, chip and package designers are eager to know the realtime temperature performance of the stacked chips therefore the workload can be assigned to the proper domain. Hence, a thermal test chip for evaluating the package is proposed in this paper. The thermal sensor network based on a ring oscillator is implemented in this work. Infrared radiation microscopic is employed for inspecting the real-time temperature performance of the chip and package. Four types of package are implemented and experimented by inspection of infrared radiation thermography. The experimental results show that one of proposed design provides good temperature consistency within difference of 0.6°C with the thermal sensors. Meanwhile, the proposed package has excellent capability for evaluating thermal management of the stacked dies by providing good thermal non-uniformity by 0.035 °C/mm.