Jui-Hung Chien

Floorplanning 1024 cores in a 3D-stacked networkon- chip with thermal-aware redistribution

As the performance of a processing system is to be significantly enhanced, on-chip many-core architecture plays an indispensable role. Explorations of a suitable three-dimensional integrated circuit (3D IC) with through-silicon via (TSV) to realize a large number of processing units and highly dense interconnects certainly attract the attention. However, the combination of processors, memories, and/or sensors in a die stack leads to the cooling problem in a tottering situation. Consequently, a thermal solution which has a high heat removing rate seems unavoidable. The floorplan and routing of the chip should be rearranged after the thermal solution is performed. By utilizing the thermal ridge, the routing spaces between hot core-groups (CGs) need to be expanded until they cannot affect each other. Under the constraint of 20% area overhead for the thermal ridges, we place the thermal ridges with different densities of thermal TSVs between the hottest CGs on the chip. For a 1024-core network on chip (NoC) design studied in this paper, the maximum temperature decreases from 408 K to 372 K, and the temperature nonuniformity is improved from 3.8 K/cm to 0.5∼1.5 K/cm. This means that the temperature difference between two neighboring CGs is less than 0.06 K. Compared with micro-fluidic cooling channel, the proposed thermal ridge scheme is much more costeffective and easy to implement.

Contactless Stacked-die Testing for Pre-bond Interposers

A stacked-die product integrates multiple dies on interposers. In this paper, we first discuss the difficulties of traditional testing mechanism for interposers. To improve production yield, a contactless testing mechanism for pre-bond interposers is proposed. Our testing mechanism attempts to detect a defective interposer from the thermal image after heating the interposer. We propose to extract special features from the thermal image and then use a clustering algorithm to determine whether the interposer is defective. Experimental results show that our testing mechanism can efficiently improve the yield from 70.5% to 96.84%.

TSV fault-tolerant mechanisms with application to 3D clock networks

Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. Through Silicon Via (TSV) formation is one of the key enabling technologies for 3D ICs. While TSVs provide vertical connections between different dies for higher performance, they suffer from random open defects and thermo-mechanical stress. The potential yield loss can significantly increase the mass production cost, which in turn affects the profitability of 3D ICs. To address the TSV reliability issues, double TSV, shared spare TSV and TSV fault tolerant unit (TFU) techniques have been developed. In this paper, we briefly review them and use 3D clock networks as a vehicle to compare their effectiveness and overhead.

On the futility of thermal through-silicon-vias

Thermal integrity is one of the most important challenges faced by three-dimensional integrated circuits (3D ICs). Towards this, thermal through-silicon-vias (TTSVs) have been widely used to assist heat dissipation. The metal inside TTSVs can conduct heat more effectively than the silicon substrate, and the metal bumps underneath TTSVs can help heat penetrate through the inter-layer thermal interface material (TIM). However, the surrounding silicon dioxide blocks the heat flowing into them. This makes the effectiveness of TTSVs questionable. In this paper, we argue that some existing TTSV models fail to capture those effects. Experimental results based on finite element simulations verify and confirm that the temperature reduction is indeed brought by the metal bumps underneath the TTSVs rather than the TTSVs themselves. We demonstrate that it is sufficient to add bumps between tiers to reduce temperature without wasting silicon area.

Simultaneous Quantification for Hepatitis B Virus and Hepatitis C Virus Using Real-time PCR Lab-on-a-chip

The current real-time PCR (polymerase chain reaction) platforms, which can detect and quantify several target DNA simultaneously, are equipped with discrete optics and detectors for different fluorescence wavelengths. However, the optical loss, due to the different lengths of the channels for several dyes, lowers the performance of fluorescence detection. Especially on the PCR platforms of lab-on-a-chip system, for the dispersion of the fluorescence in the micro fluidic channels, the received fluorescence is much lower than the emitted. To enhance the received intensity on the detection system is therefore a critical issue. The proposed fluorescence detection system, composing of an ultra-sensitive spectrometer, can provide continuous wavelength detection and can be employed for multiple DNA quantification and genotyping in a single reaction. For the tests to the genotyping ability, the melting temperatures of B type HBV and C type HBV can be distinguished by the difference of 1.1degC.The test results in this research show the same degree of sensitivity for DNA quantification and reproducibility within five intra assay samples as compared with a commercial one

Thermal stress aware design for stacking IC with through glass via

Stacking die technology using interposer with through-substrate-via technology has attracted a lot of attention due to various advantages in performance and integration. Interposers with through-glass-vias (TGVs) are widely studied due to their excellent electrical properties. However, a high temperature environment during the fabrication process of TGV leads to uncontrollable thermal expansion, which then causes a serious reliability problem. In this paper, we present an efficient algorithm to place micro bumps to reduce stress surrounding TGVs in appropriate positions that can minimize the total number of micro bumps needed. Our simulated results show that significant reduction on the maximum stress can be achieved. Not only the proposed design can lower the maximum temperature of the hotspot, but improve the thermal uniformity of the test chip.

Design and implementation of 3D-thermal test chip for exploration of package effects

Thermal solution and thermal management are critical issues in either 2.5D or 3D stacking design, especially when the hotspots are not located next to the heat sink. On the other hand, chip and package designers are eager to know the realtime temperature performance of the stacked chips therefore the workload can be assigned to the proper domain. Hence, a thermal test chip for evaluating the package is proposed in this paper. The thermal sensor network based on a ring oscillator is implemented in this work. Infrared radiation microscopic is employed for inspecting the real-time temperature performance of the chip and package. Four types of package are implemented and experimented by inspection of infrared radiation thermography. The experimental results show that one of proposed design provides good temperature consistency within difference of 0.6°C with the thermal sensors. Meanwhile, the proposed package has excellent capability for evaluating thermal management of the stacked dies by providing good thermal non-uniformity by 0.035 °C/mm.

Cyber physical system (CPS) for contactless IC testing

In this paper, we study the testing flow in fabrication process of stacked-die products. We discuss the difficulties of traditional testing mechanism. To improve production yield, a contactless testing with cyber physical system (CPS) for pre-bond interposers is proposed in this paper. We propose a testing framework comprising a heating laser and an infrared-radiation camera. In addition, we also build a completely correct model of a functional interposer. By our proposed Classification Algorithm and BDA classifier, functional and defective interposers can be differentiated. Our experimental results show that the proposed framework provides an over 97% accuracy to identify functional interposers from a whole batch of untested products.

Package geometric aware thermal analysis by infrared-radiation thermal images

Since packages affect the amount of heat transfer, it is important to include package and heat sink in thermal analysis. In this paper, we study the full-chip thermal response with different packages. We first discuss the difficulties of obtaining accurate package models for simulation. To facilitate a designer to perform thermal simulation with different packages, we propose to use a matrix called the package-transfer matrix which can transform a temperature profile of one package to another temperature profile of the desired package. To estimate and verify a package-transfer matrix, we propose an efficient method which uses Infrared Radiation (IR) images from two carefully design test chips with PBGA packages. Our experimental results show that the default package model CBGA in HotSpot can be accurately transferred to any other package through the package-transfer matrix.

Hybrid thermal solution for 3D-ICs: Using thermal TSVs with placement algorithm for stress relieving structures

Stacking die technology using through-silicon-via (TSV) technology has attracted a lot of attention due to various advantages in performance and integration. However, a high temperature environment during the fabrication process of TSV leads to uncontrollable thermal expansion, which then causes a serious reliability problem, the thermal mechanical problem. This problem can result in deformation or mechanical damage to the dies; therefore, it must be resolved. Unlike previous works applying novel components which are not in the standard CMOS process and thus potentially very expensive, this paper proposes to use package process compatible component, micro bumps, to relax the thermal mechanical stress. In addition, we present an efficient algorithm to place micro bumps in appropriate positions to minimize the total number of micro bumps needed. Our simulated results show that significant reduction on the maximum stress can be achieved. Not only the proposed design can lower the maximum temperature of the hotspot, but improve the thermal uniformity of the test chip. Finally, the infrared radiation thermal images are employed for monitoring the temperature of the virtual cores and that of the hybrid thermal solution. The experimental results show that one of proposed design provides excellent capability for enhancement of thermal conduction.