Chien Hung Kuo

A Low-Voltage Fourth-Order Cascade Delta–Sigma Modulator in 0.18-

In this paper, a low-voltage fourth-order 2-2 cascade delta-sigma (ΔΣ) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the ΔΣ modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order ΔΣ modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented ΔΣ modulator is fabricated in a 0.18- μm 1P6M CMOS technology. The chip core area without PADs is 1.57 mm2 . The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance.

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In this paper, two CMOS oversampling delta-sigma (/spl Delta//spl Sigma/) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) /spl Delta//spl Sigma/ modulator. The second one directly uses the MOP to realize a first-order SC /spl Delta//spl Sigma/ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-/spl mu/m CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least /spl plusmn/100 mT. The gain errors within /spl plusmn/100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 /spl mu/T for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectively.

CMOS

This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

CMOS oversampling /spl Delta//spl Sigma/ magnetic-to-digital converters

In this paper, a CMOS magnetic field to frequency converter with high resolution is presented. It is composed of two voltage-controlled ring oscillators whose output frequency differences linearly vary with the magnetic field perpendicular to the chip surface. The prototype circuit has been fabricated in a 0.5-/spl mu/m CMOS process and operated at a 5-V supply voltage. The measured sensitivity is 24 kHz/mT and the power consumption is 5.1 mW. The small equivalent resolution of at least 20 /spl mu/T can be achieved. The frequency offset is 42 kHz when no magnetic field applied. Its nonlinearity within /spl plusmn/120 mT is smaller than 0.56%.

A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

In this paper, a fast-locking delay-locked loop (DLL) with jitter-bounded feature is presented. In the proposed fast-locking mechanism, a frequency estimator and a programmable voltage circuit are developed to rapidly switch the control node of voltage-controlled delay line to a voltage level near the final required value. After that, the DLL output will be quickly locked by the following charge pumping on the loop filter. In the jitter-bounded approach, two phase-frequency detectors and a tunable delay are employed to hold the output clock jitter between two reference inputs after the DLL is locked. Furthermore, to enhance the flexibility of the presented DLL, a frequency multiplier with fewer active devices is also developed to provide high-frequency clock output for wideband applications. The presented DLL is implemented in a 0.18-μm 1P6M CMOS technology. The active area without contact pads is 0.34 × 0.41 mm2. A minimum lock time of six clock cycles is measured from no reference input to locked state. The output frequency ranges of the DLL and the frequency multiplier can be measured from 200 to 400 MHz and from 1 to 2 GHz, respectively. The power dissipation of the presented DLL is 31.5 mW at a 1.8 V supply voltage.

CMOS magnetic field to frequency converter

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-/spl mu/m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.

A multi-band fast-locking delay-locked loop with jitter-bounded feature

A tunable switched-capacitor (SC) bandpass delta sigma (/spl Delta//spl Sigma/) modulator using double sampling by one input parameter is proposed. The center frequency of the modulator can be varied from fs/14 to 6fs/14 at a sampling frequency (fs) of 70 MHz. Its performance can be hence improved by fine tuning the center frequency. The purposed modulator was implemented in 0.35-/spl mu/m 2P4M CMOS standard technology with the core area of 4.2 mm/sup 2/. The measured dynamic range of 68 dB within 200 kHz bandwidth can be achieved. Its power consumption is 58 mW under a 3.3-V supply voltage.

A 1-V 10.7-MHz fourth-order bandpass /spl Delta//spl Sigma/ modulators using two switched op amps

This paper presents a 0.8 V multibit delta-sigma (DeltaSigma) modulator with a single switched-opamp (SOP) in a 0.18 mum 1P6M CMOS technology. The double-sampling technique is adopted in the modulator to promote the clock efficiency and relax the requirement of SOP. To improve the accuracy of the multibit quantizer in a low-voltage circumstance and reduce the static power, a new switched-capacitor (SC) multibit quantizer without R-string is proposed. The presented DeltaSigma modulator achieves a signal-to-noise-plus-distortion ratio (SNDR) of 88 dB and dynamic range (DR) of 89 dB within a 22 kHz of bandwidth under a 1.25 MHz of clock rate. The power consumption of the presented modulator is 4.2 mW at a 0.8 V of supply voltage.

A tunable bandpass /spl Delta//spl Sigma/ modulator using double sampling

In this paper, a multi-band delay-locked loop with fast-locked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the output clock jitter. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2 GHz. The presented DLL is implemented in a 0.18 mum 1P6M CMOS process. The core area excluding PADs is 0.34times0.41 mm2. The power consumption of the presented DLL is 31.5 mW at a 1.8 V of supply voltage.

An ultra low-voltage multibit delta-sigma modulator for audio-band application

A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time and nonidealities on PFD/CP. This PLL utilizes a tunable delay cell to reduce the ripple on the VCO control line and hence the jitter penalty. In addition, a fully differential delay cell for voltage-controlled oscillator (VCO) is introduced to perform a wide locking range and low-jitter performance. The proposed PLL was implemented in 0.35-/spl mu/m 2P4M CMOS standard technology with the core area of 0.1mm. It can be operated from 250MHz to 1.29GHz and consume 38.2mW of power at 1GHz under a 3.3-V supply voltage.