Chien Hung Wu

Characterization of Hf1-xZrxO2 Gate Dielectrics with 0≤x≤1 Prepared by Atomic Layer Deposition for Metal Oxide Semiconductor Field Effect Transistor Applications

In this work, we investigated the influence of incorporating zirconia (ZrO2) in HfO2 gate dielectric on the electrical properties and reliability of n-channel metal oxide semiconductor field effect transistors (nMOSFETs). Detailed film physical, chemical and optical properties of Hf1-xZrxO2 as a function of Zr content were studied using high resolution transmission electron microscopy (HR-TEM), angle resolved X-ray photoelectron spectroscopy (AR-XPS), and spectroscopic ellipsometer (SE). Compared to HfO2, Hf1-xZrxO2 provides not only higher k values for further equivalent oxide thickness (EOT) scaling but also lower capacitance–voltage (C–V) hysteresis, lower threshold voltage (Vt) shift (ΔVt), and higher time-to-failure (TTF) lifetimes. Improved TTF lifetime of as high as three orders of magnitude and 35% lower Vt shift were achieved from the Hf1-xZrxO2 gate stack with x=0.8. The improved reliability of the Hf1-xZrxO2 gate dielectric is attributed to the reduced charge trapping in the Hf1-xZrxO2 gate dielectric caused by the ZrO2 incorporation.

Comparison of equivalent oxide thickness and electrical properties of atomic layer deposited hafnium zirconate dielectrics with thermal or decoupled plasma nitridation process

The NH3 thermal annealing and decoupled plasma nitridation (DPN) processes are compared for the equivalent oxide thickness (EOT) scaling of atomic-layer-deposited hafnium zirconate (HfZrO2) gate dielectric. Detailed physical, optical, and electrical characteristics of nitrided HfZrO2 (HfZrON) film are reported. It is found that DPN can yield a thinner SiOx interfacial layer (IL) (about 0.12 nm more in terms of EOT scaling) and a more densified HfZrO2 layer compared to those obtained using NH3 thermal annealing at a 16% nitrogen dose. NH3 thermal nitridation causes a large nitrogen distribution tail at the SiOx IL/Si substrate interface and increases leakage current, which suppresses EOT scalability.

Improving source/drain contact resistance of amorphous indium–gallium–zinc-oxide thin-film transistors using an n+-ZnO buffer layer

To avoid high temperature annealing in improving the source/drain (S/D) resistance (R DS) of amorphous indium–gallium–zinc-oxide (α-IGZO) thin-film transistors (TFTs) for flexible electronics, a simple and efficient technique using a sputtering-deposited n+-ZnO buffer layer (BL) sandwiched between the S/D electrode and the α-IGZO channel is proposed and demonstrated. It shows that the R DS of α-IGZO TFTs with the proposed n+-ZnO BL is reduced to 8.1 × 103 Ω as compared with 6.1 × 104 Ω of the conventional one. The facilitation of carrier tunneling between the S/D electrode and the α-IGZO channel through the use of the n+-ZnO BL to lower the effective barrier height therein is responsible for the R DS reduction. Effects of the chamber pressure on the carrier concentration of the sputtering-deposited n+-ZnO BL and the thickness of the BL on the degree of improvement in the performance of α-IGZO TFTs are analyzed and discussed.

Improvement of electrical performance of InGaZnO/HfSiO TFTs with 248-nm excimer laser annealing

The influence of 248-nm KrF excimer laser annealing (ELA) with energy density between 0 and 400 mJ/cm2 on the electrical behavior of indium gallium zinc oxide (InGaZnO) thin-film transistors (TFTs) is investigated. The experimental results show that the saturation mobility and subthreshold swing are improved from 12.4 cm2/Vs and 100 mV/dec without ELA to 17.8 cm2/Vs and 75 mV/dec, respectively, by applying a 300 mJ/cm2 laser pulse after the source/drain deposition, while maintaining an almost unchanged turn-off voltage. Such improvements are attributed to the increase in the oxygen vacancies and reduction in the bulk traps in the InGaZnO channel.

High-Mobility InGaZnO TFTs Using Atmospheric Pressure Plasma Jet Technique and 248-nm Excimer Laser Annealing

With the advantages of low apparatus cost, better suitability for large-scale fabrication, and low thermal budget, the nonvacuum atmospheric pressure plasma jet technique and 248-nm excimer laser annealing were employed for the fabrication of indium gallium zinc oxide (InGaZnO) thin-film transistors. Devices with a 150-mJ/cm2 laser demonstrated excellent electrical characteristics with reduced OFF-current, including a high channel mobility of 21.2 cm2/V-s, the ON-OFF current ratio of 7 × 105, and a subthreshold swing of 0.48 V/decade. The improvements are attributed to the increase of oxygen vacancies in the InGaZnO channel and the reduction of traps at the ZrO2/InGaZnO interface and InGaZnO bulk.

Improving Crystalline Silicon Solar Cell Efficiency Using Graded-Refractive-Index SiON/ZnO Nanostructures

The fabrication of silicon oxynitride (SiON)/ZnO nanotube (NT) arrays and their application in improving the energy conversion efficiency (η) of crystalline Si-based solar cells (SCs) are reported. The SiON/ZnO NT arrays have a graded-refractive-index that varies from 3.5 (Si) to (Si3N4 and ZnO) to (SiON) to 1 (air). Experimental results show that the use of 0.4u2009μm long ZnO NT arrays coated with a 150u2009nm thick SiON film increases by 39.2% under AM 1.5u2009G (100u2009mW/cm2) illumination as compared to that of regular SCs with a Si3N4/micropyramid surface. This enhancement can be attributed to SiON/ZnO NT arrays effectively releasing surface reflection and minimizing Fresnel loss.

Improvement on Interface Quality and Reliability Properties of HfAlOx MIS Capacitor with Dual Plasma Treatment

a Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan 30010, R.O.C. b College of Electrical and Information Engineering, I-Shou University, No.1, Sec. 1, Syuecheng Rd., Dashu Township, Kaohsiung County, Taiwan 84001, R.O.C. c Dept. of Electronics Eng., Chung Hua Univ., Hsinchu, Taiwan707, Sec. 2, Wufu Road, d Department of Electronic Engineering, Technology and Science Institute of Northern Taiwan, 2 Xueyuan Road, Taipei, Taiwan, R.O.C.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1− x O2 Gate dielectric and improved electrical and hysteresis performance

The use of co-sputtered zirconium silicon oxide (Zr x Si1− x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0–150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1− x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V−1 s−1).

The investigation for In-Ga-Zn-O TFTs with post deposition of in-situ Ar/H 2 plasma treatment by atmospheric pressure plasma Jet

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) was applied for the fabrication of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs). In this work, a-IGZO TFTs fabricated by AP-PECVD technique were firstly treated by post deposition of in-situ Ar/H₂ plasma with atmospheric pressure plasma Jet (APPJ). Compared to without plasma treatment, samples with the post in-situ Ar/H₂ plasma treatment on IGZO active layer exhibited higher mobility of 20.12 cm²/V·S, V_T of 1.11 V, lower subthreshold swing of 93 mV/decade, higher I_on/I_off of 5.34×10⁷. The excellent IGZO TFTs fabricated by AP-PECVD technique also show highly transparent characteristics.

Using co-sputtered ZrSiO x gate dielectrics to improve mobility and subthreshold swing of amorphous IGZO thin-film transistors

In recent years, amorphous indium-gallium-zinc-oxide (α-IGZO) thin-film transistors (TFTs) with much better performance compared with the low-temperature polysilicon (LTPS) counterpart have been demonstrated [1-2], nevertheless, continuous efforts are still urged to further polish its electrical properties for display application. To strengthen field effect and reduce gate leakage current, many research works have been focused on the feasibility of other alternative high-κ dielectric for α-IGZO TFTs [3]. In the present work, the use of co-sputtered zirconium silicon oxide (ZrSiO_x) gate dielectrics to improve both mobility and subthreshold swing (SS) of α-IGZO TFT is proposed and demonstrated. The ZrSiO_x dielectric is expected to have a good compromise between the field effect (κ-value) and gate leakage current, because silicon dioxide (SiO₂) is with the widest bandgap and zirconium dioxide (ZrO₂) could have a much better interface with α-IGZO in comparison with hafnium dioxide (HfO₂) [4]. The suitable RF power ratio for the co-sputtering of ZrO₂ and SiO₂ targets at room temperature to maximize the role of ZrSiO_x dielectrics is investigated. Immunity of poly-structure formation of the ZrSiO_x dielectrics with RF power ratio (ZrO₂:SiO₂) > 2 found in experiments is examined. In addition, effect of post annealing after dielectric deposition (PA) on device performance are also studied.