Chih-Han Chen

Electroluminescence from n-ZnO nanowires/p-GaN heterostructure light-emitting diodes

The investigation explores the fabrication and characteristics of ZnO nanowire (NW)/p-GaN/ZnO NW heterojunction light-emitting diodes (LEDs). Vertically aligned ZnO NWs arrays were grown on the p-GaN substrate. The n-p-n heterojunction LED was fabricated by combining indium tin oxide/glass substrate with the prepared ZnO NWs/p-GaN substrate. The symmetrical rectifying behavior demonstrates that the heterostructure herein was formed with two p-n junction diodes and connected back to back. The room-temperature electroluminescent emission peak at 415 nm was attributed to the band offset at the interface between n-ZnO and p-GaN and defect-related emission from ZnO and GaN. Finally, the photograph indicated the LED clearly emitted blue light.

Wide angle distributed Bragg reflectors for 590 nm amber AlGaInP light-emitting diodes

A structure for high brightness light-emitting diodes (LEDs) is demonstrated. A distributed Bragg reflector (DBR) is used to enhance the quantum efficiency of the LEDs. This unique DBR uses a composite structure that consists of two DBRs to provide both high reflectivity and wide angle reflection. For 590 nm (amber range) AlGaInP LEDs, the quantum efficiency is increased to 5.05% by using this composite DBR structure. This result is much better than those obtained from conventional DBRs, and is comparable to that of wafer bonded AlGaInP LEDs.

Study and improvement of anomalous interface states of metal‐oxide‐semiconductor structures induced by rapid thermal post‐oxide annealing

Anomalous interface states were caused by post‐oxide rapid thermal annealing in an n+ polycrystalline silicon metal‐oxide‐semiconductor capacitor. These anomalous interface states have been investigated using high/low frequency capacitance/gate voltage (C/V) measurements. An additional annealing process (450u2009°C, 30 min in 90% N2/10% H2 mixed gas) was found to improve the anomalous interface states. The improved results were identified using a constant current injection stress test.

Characteristics of MOS capacitors of BF/sub 2/ or B implanted polysilicon gate with and without POCl/sub 3/ co-doped

The characteristics of BF/sub 2/- or B-implanted polysilicon gate MOS capacitors with and without POCl/sub 3/ codoped were studied. It was found that the gate oxide thickness was increased very significantly with the number of high-temperature thermal cycles for BF/sub 2/-implanted polysilicon MOS capacitors, but this was not true for POCl/sub 3/-codoped polysilicon MOS capacitors. A model that interprets this phenomenon well was developed using the results of SIMS (secondary ion ion mass spectrometry) measurements.<<ETX>>

Rapid thermal annealing and the anomalous threshold voltage shift of metal‐oxide‐semiconductor structure in n+ polycrystalline silicon gate complementary metal‐oxide‐semiconductor technology

An anomalous different threshold voltage shift between P‐channel metal‐oxide‐semiconductor field effect transistor (P‐MOSFET) and N‐channel MOSFET under high temperature rapid thermal annealing (RTA) borophosphosilicate glass reflow has been studied using 1 μm n+ polygate complementary MOS technology. The boron transient enhanced outdiffusion and phosphorus pileup at channel surface, as well as the interface states generated due to the degradation of thin gate oxide under high RTA process, are proposed as the main sources of this anomalous shift. A detailed model is proposed to interpret the mechanism and some methods to solve the anomalous shift are suggested.

The origins of the performance degradation of implanted p/sup +/ polysilicon gated p-channel MOSFET with/without rapid thermal annealing

Some anomalous behaviors, such as punchthrough voltage reduction, leakage current increase, and transconductance (g/sub m/) instability have been found in BF/sub 2/ implanted p/sup +/-polysilicon P-MOSFETs. These effects are supposed to be due to B-ion penetration. To prevent the B-ion penetration, RTA has been used. Experimental results show that RTA can improve the effect, however, the RTA process can also cause the generation of interface states, gate-induced-drain-leakage increase, and oxide quality degradation. All of the mechanisms of performance degradation are investigated and modeled in detail. >

The anomalous threshold voltage shift of N- and P-MOSFET under flow and reflow of BPSG film with RTA and/or furnace

Different post oxide annealing technologies, i.e. furnace and/or RTA were done in borophosphosilicate glass (BPSG) films under flow and reflow. It is found that the threshold voltage shift is apparent in P-MOSFET but small in N-MOSFET for a device with RTA reflow. Base on the charge pumping measurement, the donor-type interface states generated by RTA reflow process are supposed to play a major role in this shift. The authors explain the mechanism of RTA induced donor-like interface states in detail. >

Effect of rapid thermal annealing on gate induced drain leakage in a n‐channel metal‐oxide‐semiconductor field effect transistor

Significant gate induced drain leakage caused by post‐oxide rapid thermal annealing (RTA) was studied in this letter in comparison with the non‐RTA process for n‐channel metal‐oxide‐ semiconductor field effect transistor. It is found that the sub‐breakdown leakage increases with increasing RTA temperature. We proposed that interface states and recombination centers generated after RTA are the dominant factors in the enhancement of the leakage current. In addition, it is found that RTA has no effect on the avalanche breakdown voltage.