J.C. Hsieh

Diamond deposition from halogenated methane reactants in a hot‐filament chemical vapor deposition reactor

The growth behavior of diamond films synthesized from halomethane reactants is studied in a hot‐filament chemical vapor deposition reactor. The growth characteristics of methane and several chloromethane reactants (CH2Cl2, CHCl3, and CCl4) are examined over a number of reactant concentrations, substrate temperatures (700–900 °C), reactor pressures, and filament temperatures. The results indicate that in comparison to methane, chloromethane reactants generally yield higher rates of diamond film growth, with this difference becoming more pronounced at lower substrate temperatures. As a result, chloromethane reactants possess potential in facilitating diamond growth at low growth temperatures. Possible explanations for this behavior involving gas phase and surface reaction mechanisms of chloromethane reactants are proposed.

Low-temperature deposition of diamond using chloromethane in a hot-filament chemical vapor deposition reactor

Abstract Chloromethanes (CH 2 Cl 2 , CHCl 3 and CCl 4 ) were used as carbon sources to grow diamond at low temperature (from 380°C to 700°C). In comparison with methane, which is inefficient at growing diamond below 600°C, chloromethane was quite suitable for the growth of diamond films at low temperature. Diamond growth was possible even at 380°C, which was the lowest temperature possible in the system utilized here, using CCl 4 reactant. Scanning electron micrographs, X-ray diffraction patterns and Raman spectra confirmed the presence of diamond crystallites. However, the growth rate at 380°C was only 0.05 μm h −1 . Improved growth rates were achieved with hydrogen passing through the hot-filament and carbon source gas bypassing the filament (bypass configuration). The growth rate of diamond was indeed enhanced very significantly using chloromethane in the bypass configuration. However, problems such as non-uniform growth and a narrow range of possible growth parameters arose using the bypass configuration. In contrast, the growth rate was not enhanced by using methane in the bypass configuration. The advantages of chloromethane are demonstrated. Possible reasons for such advantages are also discussed.

Study and improvement of anomalous interface states of metal‐oxide‐semiconductor structures induced by rapid thermal post‐oxide annealing

Anomalous interface states were caused by post‐oxide rapid thermal annealing in an n+ polycrystalline silicon metal‐oxide‐semiconductor capacitor. These anomalous interface states have been investigated using high/low frequency capacitance/gate voltage (C/V) measurements. An additional annealing process (450 °C, 30 min in 90% N2/10% H2 mixed gas) was found to improve the anomalous interface states. The improved results were identified using a constant current injection stress test.

Characteristics of MOS capacitors of BF/sub 2/ or B implanted polysilicon gate with and without POCl/sub 3/ co-doped

The characteristics of BF/sub 2/- or B-implanted polysilicon gate MOS capacitors with and without POCl/sub 3/ codoped were studied. It was found that the gate oxide thickness was increased very significantly with the number of high-temperature thermal cycles for BF/sub 2/-implanted polysilicon MOS capacitors, but this was not true for POCl/sub 3/-codoped polysilicon MOS capacitors. A model that interprets this phenomenon well was developed using the results of SIMS (secondary ion ion mass spectrometry) measurements.<<ETX>>

Rapid thermal annealing and the anomalous threshold voltage shift of metal‐oxide‐semiconductor structure in n+ polycrystalline silicon gate complementary metal‐oxide‐semiconductor technology

An anomalous different threshold voltage shift between P‐channel metal‐oxide‐semiconductor field effect transistor (P‐MOSFET) and N‐channel MOSFET under high temperature rapid thermal annealing (RTA) borophosphosilicate glass reflow has been studied using 1 μm n+ polygate complementary MOS technology. The boron transient enhanced outdiffusion and phosphorus pileup at channel surface, as well as the interface states generated due to the degradation of thin gate oxide under high RTA process, are proposed as the main sources of this anomalous shift. A detailed model is proposed to interpret the mechanism and some methods to solve the anomalous shift are suggested.

Growth of diamond film by a plug-flow flat flame method

Abstract The conventional acetylene-oxygen mixture torch flame can grow diamond film at fast rates, but it suffers from problems such as small area coverage, non-uniform growth, and poor reproducibility due to the large concentration and temperature gradients. Considering the effects of momentum, heat and mass transfer in the flame, we proposed to study diamond growth by the plug-flow flat flame method. Our results indicated that, owing to the large burning velocity of the acetylene-oxygen mixture, dilution was required for resonable gas consumption. The growth of uniform diamond films by a flat flame method was successful. Dilution, however, reduced the growth rate of diamond significantly and the crystal qualities deteriorated. The effects of dilution gases were studied by comparing nitrogen and argon. Argon was more favorable for diamond growth than nitrogen. The possible reasons will be discussed.

The origins of the performance degradation of implanted p/sup +/ polysilicon gated p-channel MOSFET with/without rapid thermal annealing

Some anomalous behaviors, such as punchthrough voltage reduction, leakage current increase, and transconductance (g/sub m/) instability have been found in BF/sub 2/ implanted p/sup +/-polysilicon P-MOSFETs. These effects are supposed to be due to B-ion penetration. To prevent the B-ion penetration, RTA has been used. Experimental results show that RTA can improve the effect, however, the RTA process can also cause the generation of interface states, gate-induced-drain-leakage increase, and oxide quality degradation. All of the mechanisms of performance degradation are investigated and modeled in detail. >

The anomalous threshold voltage shift of N- and P-MOSFET under flow and reflow of BPSG film with RTA and/or furnace

Different post oxide annealing technologies, i.e. furnace and/or RTA were done in borophosphosilicate glass (BPSG) films under flow and reflow. It is found that the threshold voltage shift is apparent in P-MOSFET but small in N-MOSFET for a device with RTA reflow. Base on the charge pumping measurement, the donor-type interface states generated by RTA reflow process are supposed to play a major role in this shift. The authors explain the mechanism of RTA induced donor-like interface states in detail. >

Effect of rapid thermal annealing on gate induced drain leakage in a n‐channel metal‐oxide‐semiconductor field effect transistor

Significant gate induced drain leakage caused by post‐oxide rapid thermal annealing (RTA) was studied in this letter in comparison with the non‐RTA process for n‐channel metal‐oxide‐ semiconductor field effect transistor. It is found that the sub‐breakdown leakage increases with increasing RTA temperature. We proposed that interface states and recombination centers generated after RTA are the dominant factors in the enhancement of the leakage current. In addition, it is found that RTA has no effect on the avalanche breakdown voltage.

Extra interface state generation enhanced by fluorine in tungsten‐polycided metal‐oxide‐semiconductor devices with nitrided oxide gate dielectric

Interface state generation in oxynitride gate dielectric devices with tungsten‐polycide (W‐polycide) and polycrystalline silicon (poly‐Si) gate structures were investigated. A significant amount of fluorine‐induced interface states were detected in W‐polycide gate device with nitridation of thermal gate oxide by both the charge pumping technique and capacitance/gate voltage (C/V) measurement. Re‐oxidation of oxynitride gate oxide results in partial annealing of these interface states. A model of the fluorine induced strain gradient between silicon dioxide and silicon (SiO2/Si) interface was proposed to explain the extra interface state generation mechanism.