Y.K. Fang

The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 μm CMOS technology and beyond

The authors report the effect of the remote plasma nitridation (RPN) process on characteristics of ultrathin gate dielectric CMOSFETs with the thickness in the range of 18 /spl Aring//spl sim/22 /spl Aring/. In addition, the effect of RPN temperature on the nitrogen-profile within the gate dielectric films has been investigated. Experimental results show that the thinner the gate dielectric films, the more significant effect on reducing the gate current and thinning the thickness of gate dielectric films by the RPN process. Furthermore, the minimum dielectric thickness to block the penetration of B and N has been estimated based on the experimental results. The minimum RPN gate dielectric thickness is about 12 /spl Aring/.

Narrow width effects of bottom-gate polysilicon thin film transistors

The effects of channel width on the characteristics of both hydrogenated and unhydrogenated bottom-gate polysilicon thin-film transistors (TFTs) were investigated in detailed. For unhydrogenated and silane gas formed TFTs, a drastic decrease in threshold voltage is observed due to the grain-boundary traps are reduced when the channel width is reduced to less than grain size, but the minimum drain current sensitive to intragranular tail states are nearly unchanged. After hydrogenation, almost grain boundary traps and intragranular tail states were passivated, the effect of traps along poly channel edges caused by the definition of poly channel pattern will dominate, i.e., threshold voltage and minimum drain current increase with decreasing channel width. Also disilane gas formed TFTs are studied for comparison.

The anomalous behavior of hydrogenated/unhydrogenated polysilicon thin-film transistors under electric stress

The characteristics of high-temperature processed thin-film transistors (TFTs) with/without plasma hydrogenation under the stress condition of V/sub ds/=-15 V and V/sub gs/=0 V have been investigated and compared. It is found that, after stress, the subthreshold swing is greatly improved for unhydrogenated TFTs but not for hydrogenated TFTs. Also, the off-state current is deteriorated for unhydrogenated TFTs but, on the contrary, it is improved for hydrogenated TFTs. A model that takes the effect of hydrogen passivation into account is proposed to interpret the anomalous behavior of TFTs under electric stress.

To suppress UV damage on the subthreshold characteristic of TFT during hydrogenation for high density TFT SRAM

In this letter, we find an efficient way to suppress UV damage on the characteristics of polysilicon thin-film transistors (TFTs) during hydrogenation for high density TFT SRAM. Polysilicon TFT can be free from UV damage during hydrogenation if the channel region is shielded by a metal line of the same width as channel. After hydrogenation, the metal shielded TFT shows an excellent subthreshold swing of 112 mV/dec, and the leakage current can be as low as 20 fA while the unshielded TFT shows a subthreshold swing of 220 mV/dec and a leakage current of 0.33 pA. This gives almost 200% improvement in subthreshold swing and one order of magnitude reduction in leakage current.

Improvement of short-channel characteristics of a 0.1-/spl mu/m PMOSFET with ultralow-temperature nitride spacer by using a novel oxide capped boron uphill treatment

In this work, the thermal annealing at 720/spl deg/C for 2 hr (called boron uphill treatment) with an SiO/sub 2/-capped layer was applied after source/drain extensions (SDE) implantation to improve the short channel characteristics of a 0.1-/spl mu/m PMOSFET with an ultra-low temperature nitride spacer. The influence and the mechanism of the capped layer on this uphill treatment were investigated. The results show that the capped layer treatment indeed leads to a shallower junction, improved V/sub th/ roll-off characteristic, and added immunity against subsurface punchthrough.

Performance analysis and development of high-speed p-i-n infrared sensors prepared on crystalline silicon substrates

In this paper, different structures of high-speed infrared (IR) sensors based on amorphous silicon germanium and amorphous silicon hetero-structures have been successfully developed on crystalline silicon substrates. Experimental results of these developed structures exhibit a superior device performance to that of a traditional pin amorphous photo-sensor prepared on a glass substrate, especially significant improvements in the rise time from 465 (microsecond(s) ) to 195 (microsecond(s) ), and the dark current from 50 ((mu) A) to 3.3 ((mu) A) for 5 (V) reverse bias.

Investigation and modeling of stress effects on the formation of cobalt salicide

This letter studies resistance variations of the Co salicide interconnect accompanied by various surrounding in a sub-0.13-/spl mu/m CMOS technology. Our analysis shows that, during the salicidation processes, the diffusion of Co atoms and thus salicide thickness and forms of Co salicide layer are greatly affected by the stresses from surrounding structures. Moreover, variations in resistance among the various structures could exceed 100%. Thus, these stress effects were analyzed in detail based on transmission electron microscopy micrographs of Co salicide layers accompanied by four different surrounding structures.

Performance analysis and development of high-temperature B-SiC/Si optoelectronic devices with porous silicon substrate

In this paper, to suppress dark current of high temperature (beta) -SiC/Si optoelectronic device with a porous substrate has been studied. A pin structure was used to demonstrate the applicability. Experimental results show a twelve-fold improvement in optical gain at 200 degree(s)C operating temperature for the sample prepared on the porous silicon substrate as compared to the sample prepared on the silicon substrate, respectively. The improvement is attributed to the suppression of dark current by the high resistivity and flexibility of the porous substrate. A (beta) -SiC/Si optoelectronic device was fabricated both on porous silicon substrate and conventional silicon substrate, respectively. Experimental results show the optical current ratio can be improved up to 400% at room temperature and 3000% at 200 degree(s)C operating temperature, respectively, with the porous silicon substrate.

Development of electrochromic devices of tungsten oxide thin film integrated with p-i-n photodetector

In this paper, a new electro-chromic device (ECD) is developed by tungsten oxide (WO3) thin film integrated with a-Si1-xGex:H pin photodetector. With the addition of the palladium (Pd) film to ionize hydrogen gas, the WO3 thin film will react with hydrogen ion and transfer from transparency to blue color. This color change will degrade the absorption of light with wavelength larger than blue color. First, we determine the most suitable condition (by increasing the partial oxygen pressure) to produce a-WOx films, thus offering a good electro- chromic performance for opto-switching applications. Then, the photo current generated by a-Si1-xGex:H pin photodetector will be lowered down, thus detecting the existing of hydrogen gas. Especially, the WO3-pin hydrogen sensor also shows highly selectivity with hydrogen gas to separate from CO and C2H5OH gases.

Development of a pyroelectric thin film infrared sensor by micro-opto-electro-mechanical system (MOEMS) technology

An IR sensor with the lead-titanate (PbTiO3) thin-film and thermal isolation improvement structure using the technology of micro-opto-mechanical system has been designed, fabricated and developed. In this paper, both numerical analysis of the static operation mechanisms such as the effects of IR light power on the depletion layer width and voltage drop across the thin PbTiO3 film, and the dynamic responses of a thin-film pyroelectric sensor to sinusoidal modulated radiation are reported and compared to the experimental results. The fitting is quite well. The major IR-sensing par ton the cantilever beam of the developed sensor consists of a 50-nm PbTiO3 layer deposited by RF sputtering, and a gold layer evaporated as an IR radiation absorber. With active cantilever dimensions of 200 X 100 X 5 micrometers 3 formed by etching processes, the cantilever structure exhibits a much superior performances to that of a traditional IR-sensing bulk structure under the 800-(mu) W incident optical light with wavelength of 970 nm.