Chih-Jen Cheng

Systematic Design and Modeling of a OTA-C Filter for Portable ECG Detection

This study presents a systematic design of the fully differential operational transconductance amplifier-C (OTA-C) filter for a heart activities detection apparatus. Since the linearity and noise of the filter is dependent on the building cell, a precise behavioral model for the real OTA circuit is created. To reduce the influence of coefficient sensitivity and maintain an undistorted biosignal, a fifth-order ladder-type lowpass Butterworth is employed. Based on this topology, a chip fabricated in a 0.18- mum CMOS process is simulated and measured to validate the system estimation. Since the battery life and the integration with the low-voltage digital processor are the most critical requirement for the portable diagnosis device, the OTA-based circuit is operated in the subthreshold region to save power under the supply voltage of 1V. Measurement results show that this low-voltage and low-power filter possesses the HD3 of -48.9 dB, dynamic range (DR) of 50 dB, and power consumption of 453 nW. Therefore, the OTA-C filter can be adopted to eliminate the out-of-band interference of the electrocardiogram (ECG) whose signal bandwidth is located within 250 Hz.This study presents a systematic design of the fully differential operational transconductance amplifier-C (OTA-C) filter for a heart activities detection apparatus. Since the linearity and noise of the filter is dependent on the building cell, a precise behavioral model for the real OTA circuit is created. To reduce the influence of coefficient sensitivity and maintain an undistorted biosignal, a fifth-order ladder-type lowpass Butterworth is employed. Based on this topology, a chip fabricated in a 0.18- mum CMOS process is simulated and measured to validate the system estimation. Since the battery life and the integration with the low-voltage digital processor are the most critical requirement for the portable diagnosis device, the OTA-based circuit is operated in the subthreshold region to save power under the supply voltage of 1V. Measurement results show that this low-voltage and low-power filter possesses the HD3 of -48.9 dB, dynamic range (DR) of 50 dB, and power consumption of 453 nW. Therefore, the OTA-C filter can be adopted to eliminate the out-of-band interference of the electrocardiogram (ECG) whose signal bandwidth is located within 250 Hz.

A Low-Power Bidirectional Telemetry Device With a Near-Field Charging Feature for a Cardiac Microstimulator

In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.

A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems

An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a digital decimator. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the oversampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class-AB memory cell are low power consumption and high dynamic range. Moreover, a new single-multiplier structure is presented to implement the finite-impulse-response (FIR) digital filters which are the major hardware elements in the decimator. For the various applications with different biosignal frequencies, the SDADC could be manipulated in different operating modes. The overall ADC has been implemented in a TSMC 0.18-mum 1P6M standard CMOS process technology. Without a voltage booster to raise the gate voltage of switches, measurement results show that the SISDM has a dynamic range over 60 dB and a power consumption of 180 muW with an input signal of 1.25-kHz sinusoid wave and 5-kHz bandwidth under a single 0.8-V power supply for electroneurography signals. In addition, the postlayout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without degrading by digital circuits

A 1-V 8-bit 0.95mW successive approximation ADC for biosignal acquisition systems

In this paper, a 1-V 8-bit 10 kS/s successive approximation (SA) analog-to-digital converter (ADC) with ultra-low power characteristic is implemented for biosignal acquisition systems. To decrease power consumption, a passive sample-and-hold (SH) circuit and an opamp-free, capacitor-based digital-to-analog converter (DAC) are utilized. The only active circuit, a comparator, is implemented in the sub-threshold region to preserve the required bias current. According to the measured results, the ADC has a signal-to-noise distortion ratio (SNDR) of 45.2 dB, and peak spurious free dynamic range (SFDR) of 54 dB for a 1 kHz 500 mVpp input sine wave. The effective number of bits (ENOB) is 7.2. Its differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.41/+0.38 and −0.89/+0.6 LSB, respectively. The total power consumption is 950 nW, and the figure of merit (FOM) is 3230 fJ/conversion-step. The active area, which is 0.93 × 0.93 mm2, is determined by using TSMC 0.18µm 1P6M CMOS process.

Programmable pacing channel with a fully on-chip LDO regulator for cardiac pacemaker

A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-mum CMOS technology, consuming total power of 1.29 muW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a power-supply rejection ratio (PSRR) of -30 dB with the output ripple of 570 muVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 muA, LDO yields a line regulation that is less than 3% deviation.

A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme

A simple addressing scheme for pipeline MDC shared-memory architecture with mixed-radix algorithm is proposed. It can provide a simple control circuit for memory addressing generation, and the mixed-radix butterfly sequence can be automatically generated by way of simple counter. In addition, for the N-point FFT processor, only N/8 coefficients should be stored in the VLSI implementation, therefore, the ROM size and the FFT processor area are reduced. According to the simple control scheme and small memory size, the low-power VLSI architecture can be achieved. Furthermore, the architecture with the mixed-radix algorithm also enhances the speed in performing large-point FFT computations compared with the existing shared-memory architectures. Based on this architecture, not only radix-23 butterfly is adopted to achieve the requirement of high throughput, but also radix-2 2 or radix-2 butterfly is utilized to allow all of FFT calculation for N=2n. An VLSI architecture of 8192-point FFT processor with only power consumption of 890muW is also implemented to demonstrate the proposed method

Low-power signal processing devices for portable ECG detection

An analog front end for diagnosing and monitoring the behavior of the heart is presented. This sensing front end has two low-power processing devices, including a 5th-order Butterworth operational transconductance-C (OTA-C) filter and an 8-bit successive approximation analog-to-digital converter (SAADC). The components fabricated in a 0.18-μm CMOS technology feature with power consumptions of 453 nW (filter) and 940 nW (ADC) at a supply voltage of 1 V, respectively. The system specifications in terms of output noise and linearity associated with the two integrated circuits are described in this paper.

A low-voltage adaptive switched-current SDM for bio-acquisition microsystems

An ultra-low voltage and low-power adaptive switched-current sigma-delta modulator (SISDM) with a 10-bit dynamic range for bio-microsystem applications is presented. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the over-sampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class AB memory cell are low-power consumption, high linearity, and high dynamic range. For the various applications with different biosignal frequencies, the SISDM could be operated in different operation mode. The overall SDM with core area of 0.05mm2 has been implemented in a TSMC 0.18mum 1P6M standard CMOS process technology. Without voltage booster to raise the gate voltage of switches, post-layout simulation results show that the SISDM has a dynamic range over 60dB and a power consumption of 180muW with an input signal of 1.25kHz sinusoid wave and 5kHz bandwidth under a single 0.8V power supply for ENG signals

A near-field telemetry device with close-loop endocardial stimulation for a pacemaker

In this paper, a wireless telemetry using the near-field coupling technique with round-wire coils for an implanted pacemaker is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. Even with a low induced voltage, all the circuitries associated with the implantable stimulator are operated normally by the coupling power interface, which includes an efficient rectifier, one fully-integrated regulator, and a charge pump. To acquire cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs the functions of immediate threshold detection and data conversion. In addition, pacing circuits, which are responsible for stimulating heart tissue, are employed to overcome the huge voltage difference between the pulse generator (PG) and its digital-to-analog (D/A) controller. The chip is fabricated by TSMC with 0.35 µm CMOS technology to manifest the monitoring and pacing function under inductively powering communication. With a model utilizing lead and heart tissue, a-5-V pulse at a stimulating while only consuming a power of 31.5 µW.

A Low-Voltage and Area-Efficient Adaptive SI SDADC for Bio-Acquisition Microsystems

An ultra-low voltage adaptive Sigma-Delta Analog-to-Digital Converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a Switched-current Sigma-Delta Modulator (SISDM) and a digital decimator. Moreover, a new single-multiplier structure is presented to implement the Finite Impulse Response (FIR) digital filters which are the major hardware elements in the decimator. Measurement results show that the SISDM has a dynamic range over 6 dB and a power consumption of 180 muW with an input signal of 1.25 kHz sinusoid wave and 5 kHz bandwidth under a single 0.8 V power supply for ENG signals. Besides, the post layout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without harming by digital circuits.