Ming Chun Liang

Low-Power Wireless ECG Acquisition and Classification System for Body Sensor Networks

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

A Low-Power 13.56 MHz RF Front-End Circuit for Implantable Biomedical Devices

A low-power fully-integrated CMOS RF front-end circuit for a passive 13.56 MHz biomedical implant is presented. A 13.56 MHz binary phase shift keying (BPSK) signal is received by an internal coil. This front-end circuit is composed of a full-wave bridge rectifier, a linear regulator, a BPSK demodulator, and a clock/data recovery (CDR). A full-wave bridge rectifier converts the carrier waveform with the BPSK signal to an unregulated DC voltage. A linear regulator stabilizes the unregulated DC voltage to 1.8 V that serves as the DC source for the implant. A BPSK demodulator detects the incoming BPSK signal from the internal coil and translates the demodulated data to the CDR which can successfully recover the clock and data for the system controller. This chip with a core area of 0.45 mm2 has been fabricated in a TSMC 0.18 μm 1P6M CMOS technology. The total power consumed is only 632 μW.

A wireless ECG acquisition and classification system for body sensor networks

This paper demonstrates a wireless ECG acquisition and classification system with a bio-signal processor (BSP), a super regenerative transceiver, and a digital signal processor (DSP). The BSP, which is implemented with low complexity architecture, includes only a low noise amplifier with chopping techniques and a high-pass sigma-delta modulator (HPSDM). The super-regenerative on-off keying (OOK) transceiver is applied for the low power, short range transmission and low date rate wireless communication. For the signal processing and analyzing, the DSP circuit is adopted in the receiver. The whole system is implemented in a TSMC 0.18 μm 1P6M CMOS process under the supply voltage of 1.2 V. In the near body node, the power consumption including a BSP and a transmitter is 587 μW only. With two PR44 zinc-air batteries of 605 mAh, the near body node circuit can be operated about 100 days. In the receiving node, the power consumption with a receiver and a DSP is 926 μW.

FFT-based calibration method for 1.5 bit/stage pipelined ADCs

A fast Fourier transform FFT-based digital calibration method for 1.5 bit/stage pipeline analog-to-digital converter ADC is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier OPAMP can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non-ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low-gain OPAMP can be used in high-performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal-to-noise-and-distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright

ECG acquisition system with heart rate detection and energy harvesting for drivers

This paper proposes a combined heart rate detection and energy harvesting system operated on smart phones for vehicle drivers. The proposed system consists of four parts. The first part includes a high-resolution and low-power analog front-end chip to implement a biosignal sensing module (BSM). The second part comprises a digital signal processor with a high-recognition-rate QRS detection algorithm. The third part includes a power management circuit that harvests energy from a smart phone. This part provides a stable voltage supply to the BSM. The power conversion efficiency of the proposed rectifier exceeds 85%. The last part executes a data recording and heart rate variability analysis software based on the Android system. All chips are fabricated in a TSMC 0.18 μm standard CMOS process.

A 1.6uW G m -C coninuous-time sigma-delta modulator with increasing linearity technology for bio-signal acquisitions

This paper present a low-pass sigma delta modulator (LPSDM), which can be used for electroencephalogram (EEG) or electrocardiogram (ECG) signal acquisition systems. The LPSDM is implemented in continuous time Gm-C architecture and the systematic design flow is introduced. The power consumption of LPSDM is 1.614uW. According to the post-layout simulation under the bandwidth of ECG, a signal-to-noise and harmonic distortion ratio (SNDR) of 57.9 dB can be achieved.

ECG monitoring and emotion stabilization system with a physiological information platform for drivers

This study proposes an electrocardiographic (ECG) monitoring and emotion stabilization system that is composed of an acquisition system on chip and an Android system. This system has three main parts. The first part is a low-power analog front-end circuit for biosignal sensing. The second part comprises a digital signal processor for down sampling, filtering, and QRS detection. The last part is an emotion stabilization feedback control based on an Android-operated physiological information platform. This platform allows physiological information display, data recording, signal processing, and analysis. All circuits are fabricated in a TSMC 0.18 μm standard CMOS process.

Live demonstration: A wearable wireless ECG acquisition and specification system

This demonstration will present a wearable and wireless bio-signal acquisition and classification system that is specialized in electrocardiogram (ECG) monitoring. The system comprises the design and implementation with three parts, namely, an analog front-end (AFE) circuit, a digital signal processor (DSP) and the Bluetooth module. The AFE is used to detect the ECG signal and DSP is used to classify the signal and control the Bluetooth communication. At last, the real time ECG signal would be shown on the screen of the mobile phone. The system is implemented in a TSMC 0.18μm 1P6M process under supply voltage of 1.2 V. With two PR44 zinc-air batteries of 605mAh as the power supply, the system can be operated about 2 days.

Wearable electrocardiogram acquisition and classification systems with different distributive operations

This paper presents two wearable electrocardiogram signal acquisition and classification systems that are capable of long-term healthcare and bio-signal record. In the first version, an MSP430 micro-control unit (MCU) combines with low-power analog front end (AFE), and a Bluetooth module is implemented. The proposed AFE consists of a low-noise pre-amplifier with gain control and a high-pass sigma-delta modulator (HPSDM) that allows the system to achieve high resolution. The direct transmission of the HPSDM outcome can enhance data security. In the other version, the MCU is replaced by a bio-signal processor (BSP). The BSP combines a decimation filter with a wavelet-transform processor to fulfill beat detection and classification. The UART package generator is also integrated in BSP. The algorithm of BSP is verified by MIT/BIH Arrhythmia data, with sensitivity and positive predictability of 99.67% and 99.59%, respectively. The entire system can be operated for 2 days by using two PR44 zinc-air batteries of 605 mAh as power supply.

A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications

A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.