Chih-Wei Jen

SLOPE: a test pattern generator based on stop line oriented path end algorithm

The authors present a test pattern generator, SLOPE, based on the stop line oriented path end algorithm, for combinational digital circuits. It combines the advantages of FAN and FAST by utilizing a controllability measure and observability measure to assist guessing in the test generation process. With some strategies adopted in the algorithm, it generates tests with fewer number of backtrackings. Benchmark circuits run with SLOPE show that it outperforms PODEM and FAN for most circuits.<<ETX>>

Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel

In this paper, an 8X-parallelism all-digital baseband receiver is proposed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The all-digital baseband receiver contains a 4-in-1 synchronization (SYNC), a 512-point radix-23 IFFT/FFT, a phase noise cancellation (PNC), a shared memory (MEM) bank and a frequency-domain equalizer (FDE) with an optimized golay-correlator window-based noise cancellation (OGC-WNC) channel estimation (CE) for non-line-of-sight (NLOS) and line-of-sight (LOS) channels. The hardware sharing is 99% between SC and OFDM modes and the shared memory reduces memory usage by 51%. The measurement results show that the fabricated chip can provide PHY data rate of 9.24 Gb/s with power consumption of 497 mW to meet the requirement of OFDM mode for IEEE 802.15.3c and 802.11ad standards. Besides, the PHY data rate of the fabricated chip reaches 14 Gb/s with power consumption of 698 mW for OFDM mode that is beyond the standard requirement to offer higher PHY data rate over 60 GHz transmission environment.

A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver

In this paper, a novel memory access reordering polyphase network (PPN) for 60 GHz filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver is presented. The 8X-parallelism architecture of PPN is integrated into our 8X-parallelism digital baseband receiver. The PPN is designed based on IEEE 802.15.3c and IEEE 802.11ad standards. The PPN contains three key modules including memory bank, filter coefficient selector and 4-tap PPN filter. The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process. The implementation result shows it can operate at specified 330/500 MHz clock rate with power consumption of 17/26 mW at 0.81 V supply voltage. With 8X-parallelism architecture, the sampling rate supports up to 2.64/4 GHz.

An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver

Filter bank multi-carrier (FBMC) is a kind of new waveform that is an important topic in 5th generation wireless systems (5G). In this paper, we propose a novel memory access reordering polyphase network (PPN) for FBMC offset QAM (OQAM) system at 60 GHz band. The novel PPN architecture has lower complexity than the state-of-the-art designs, and it can be used in any FBMC-OQAM baseband design. To evaluate the system performance and hardware complexity of baseband receiver in millimeter wave (mmW) band, the proposed PPN is integrated into our 8X-parallelism 60 GHz band baseband receiver. The out-of-band (OOB) radiation in fixed-point simulation has 25 dB improvement as compared with OFDM. Furthermore, the transmission efficiency of FBMC-OQAM baseband receiver can improve 52% due to using more data subcarriers and removal of cyclic prefix (CP). The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process, and can operate at 330/500 MHz clock rate with power consumption of 17/26 mW, providing the maximum PHY data rate up to 21.4 Gb/s.

Interference measurement and analysis of full-duplex wireless system in 60 GHz band

With co-time co-frequency full duplex (CCFD) in 60 GHz band, self interference (SI) has different characteristics due to larger wireless path loss and beamformed system compared to current band under 6 GHz (normal band). In this paper, we present real SI channel measurement results and analysis to consider indoor CCFD in 60 GHz band. The results show that the narrow beam antennas can effectively suppress the direct leakage component but increase the root mean square (RMS) delay spread of the SI channel due to reflections from nearby objects. The effect of phase noise on SI cancellation is demonstrated since a high-frequency oscillator is used. At the end, we show the key factors of SI cancellation based on the measurement results for implementation of CCFD in 60 GHz band.

A multi-phase shared bus structure for the fast Fourier transform

The multi-phase shared bus structure is proposed for the implementation of the complex data flows in fast Fourier transforms (FFTs). With multiphase techniques, the executions of the pipelines are time-skewed. Data communications between pipeline stages can be multiplexed via the shared bus. The routing area is small and independent of the routing complexity. For the 8-point butterfly at 100 MHz data rate, multi-phase implementation needs only 30% area compared to direct routing. By proper phase assignment, the processing latency can also be reduced. The latency of the 8-point FFT design example is reduced to 68%. The communication cost of the direct implementation and the proposed structure is estimated and compared.<<ETX>>

A CORDIC-based VLSI array for computing 2D discrete Hartley transform

The inseparability of the 2D discrete Hartley transform (DHT) makes its VLSI design and hardware realization much more expensive. To solve this problem, a new CORDIC-based 2D DHT algorithm and the associated array design are presented. By exploiting the CORDIC (coordinate rotations digital computer) property, the row/column decomposition can be successfully applied to reduce the computational complexity enormously without paying decomposition overhead. The array features systolic computing style, the CORDIC structure of processing elements (PEs), low input/output (I/O) cost, and simple hardware.<<ETX>>

The Kalman filter design by systolic arrays with tag input

An array design based on a novel architecture called SATIN is presented which can perform matrix operations efficiently. SATIN is one kind of systolic array incorporating a control scheme which can solve the stored-I/O and time-invariant function problems efficiently and completely. Standard Kalman filter formulation is rearranged such that the number of matrix operations can be reduced and the execution sequence is suitable for executing concurrently by SATIN. This design not only provides computation efficiency but also has other advantages, such as simplicity of PE realization and complete consideration of control.<<ETX>>

Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band

In this paper, we propose a tracking mechanism for the residual sampling clocking offset (SCO) with corresponding pilot and auxiliary pilot arrangements for filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver in the 60 GHz band. This work can effectively compensate the non-ideal effects on the high-band subcarriers while using more data subcarrier for increasing bandwidth efficiency. This work is designed based on IEEE 802.15.3c and IEEE 802.11ad standards and synthesized with 40 nm 1P9M general purposes (GP) process. The proposed SCO tracking module with the proposed alternated pilot and auxiliary pilot arrangement can improve the BER floor and reach to 10−2 at SNR of 22 dB which is only 1.75 dB more than that of no SCO effect in 64-QAM modulation.

A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band

In this paper, a minimum mean square error (MMSE) joint feedback feed-forward equalizer (MJFFE) is proposed to deterministically suppress the inter-symbol interference and inter-carrier interference that arose from the filter bank multi-carrier in a long multipath channel of the 60-GHz indoor wireless transmission. The decision device is discarded in the decision feedback loop to reduce error propagation while at the same time applying the MMSE criterion to prevent over compensation influenced by additive white Gaussian noise. As a result, in an non-line-of-sight (NLOS) channel with 7.65-ns rms delay spread, a 3-tap MJFFE provides 3-dB improvement at the bit error rate (BER) 10−2 crossing and improve error floor effect at the BER 10−3 crossing, as compared with the 1-tap zero-forcing equalizer. Furthermore, the proposed equalizer coefficients calculation based on linear convolution for the MJFFE is also presented. The hardware complexity achieves 50% reduction by using several methods including multiplexing, memory sharing, and computation element sharing.