Chilgee Lee

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area- efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 m with under 1uW power consumption for providing 0.7degC effective resolution at 1 sample/sec processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

A slew-rate-controlled output driver having a constant transition time irrespective of environmental variations is described in this brief. The proposed output driver employs a capacitive feedback between the output and input of the driver to allow its transition time independent of process, voltage, temperature and output load variations. The proposed output driver was designed and fabricated using a 0.13-mum CMOS process. According to our experimental results, the normalized variation on transition time of the proposed output driver due to PVT variations was improved by 74%-80% as compared to the conventional output driver. The comparison result also indicates that the normalized variation on transition time due to output load change from 10 to 100 pF (10 times variation) in typical process, voltage and temperature corners was improved by up to 66%.

On the repair of memory cells with spare rows and columns for yield improvement

As the density of memory chips increases, the probability of having defective components is also increased. It would be impossible for us to repair a memory device if it has numerous defects that cannot be dealt with properly. However, in case of a small number of defects, it is desirable to reuse a defective die (standard unit measuring a device on a wafer) after repair rather than to discard it, because reuse is an essential element for memory device manufactures to cut costs effectively. To perform the reuse, laser-repair process and redundancy analysis for setting an accurate target in the laser-repair process is needed. In this paper new approach for the repair of large random access memory (RAM) devices in which redundant rows and columns are added as spares. So, cost reduction was attempted by reducing time in carrying out a new type of redundancy analysis after simulating each defect.

A real-time face recognition system using multiple mean faces and dual mode Fisherfaces

This research features an automatic face detection and recognition system. The purpose of the system is for access control to a building or an office. The main feature of the system is face detection and face recognition robust to illumination changes. A novel template matching technique using multiple mean faces (MMF) of various sizes, luminance, and rotations is employed to achieve robust face detection. The system is also capable of operating in two different modes for face recognition: under normal illumination condition and under severe illumination changes.

Implementation of Cloud Computing Environment for Discrete Event System Simulation using Service Oriented Architecture

This paper presents a cloud computing architecture for discrete event system modeling and simulation. Simulators with models used in the cloud computing are considered as web services which are accessed via web browser. This environment supports the simulation of homogeneous or heterogeneous models without much knowledge of discrete event modeling and simulation.

A high current driving charge pump with current regulation method

This paper proposes a charge pump having a high driving capability for driving more than a load of 8 mA with a 5 V regulated output voltage. The output of the charge pump generates 5 V without any damages to the oxide using protection circuits, even though it uses 3 V MOS transistors. The prototype chip designed using 0.13 /spl mu/m CMOS process provides the range of a 0/spl sim/25 mA load current and generates a well regulated 5 V output voltage with a flying capacitor of 500 nF and clock frequency of 500 KHz. The chip area is 0.21 mm/sup 2/. The power efficiency is as much as 86% at 3.0 V supply.

CMOS cross-coupled charge pump with improved latch-up immunity

In this paper, a novel CMOS charge pump with substantially improved immunity to latch-up is presented. By utilizing a dedicated bulk pumping and blocking (DBPB) technique, the proposed charge pump achieves greatly reduced forward voltage of source/drain-substrate junction of transistors, resulting in decreased charge loss and increased latch-up immunity. Comparison results indicated that the maximum bulk forward voltage of the proposed charge pump was less than 0.05V (88% improvement) for zero output current during power-up, and less than 0.12V (88% improvement) regardless of the amount of output current during ordinary pumping operation.

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature

A slew rate-controlled output driver using capacitive feedback is described in this paper. To make a constant transition time in the output driver, a constant current source is used with capacitive feedback between output and the gate of output driver. The capacitor feedback path gives a current path which connects the gate of the output driver with the output during the output drivers transition period to sustain a constant slew rate. The proposed output driver was designed using a 0.13 /spl mu/m CMOS process. According to our evaluation, the transition time variation of the proposed output driver due to PVT variations is improved by 92% compared to the conventional output driver, and the variation due to the output load variation of 10/spl sim/100 pF in typical process, voltage and temperature condition is also improved by as much as 467 %.

Full fabrication simulation of 300mm wafer focused on AMHS (automated material handling systems)

Semiconductor fabrication lines are organized using bays, equipment, and stockers. Most 300mm wafer lines use AMHS (Automated Material Handling System) for inter-bay and intra-bay lot transportation. In particular, the inter-bay AMHS moves lots between stockers, whereas intra-bay AMHS moves lots between stockers and tools, or between tools within the same bay. The key concern for manufacturer is how to raise productivity and to reduce turn-around time. This paper presents a simulation to reduce turn around time and raise productivity by reducing the delivery time (which affects AMHS).

Effects of Ceria Abrasive Particle Size Distribution below Wafer Surface on In-Wafer Uniformity during Chemical Mechanical Polishing Processing

In this study, the abrasive size distribution of ceria-based slurry below wafer and its effect on in-wafer uniformity were examined. Based on our observation, the abrasive size varies depending on the location on the wafer. Hence process parameters such as pad surface morphology and slurry viscosity were thoroughly investigated to observe their effect on the distribution on the wafer surface. It was found that the small size particles were considerably reduced near the center location of the wafer surface during the pad lifetime with reduced slurry viscosity and high polishing pressure. Hence, the contact conditions and the characteristic of fluid should be simultaneously considered in order to obtain the stable in-wafer uniformity.