Bai-Sun Kong

Conditional-capture flip-flop for statistical power reduction

This paper describes a family of novel low-power flip-flops, collectively called conditional-capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant transitions of internal nodes. These flip-flops also have negative setup time and thus provide small data-to-output latency and attribute of soft-clock edge for overcoming clock skew-related cycle time loss. The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power savings of around 67%, as compared to conventional flip-flops. With a typical switching activity of 0.33, the power consumption is reduced by as much as 23-30% with comparable minimum data-to-output latency. It is also indicated that the proposed single-ended structure provides power comparable to the fully static master-slave design with significantly reduced data-to-output latency. An eight-bit counter was fabricated using a 0.35-/spl mu/m CMOS technology, and the experimental results indicate that the counter using the differential CCFF saves the overall power consumption by about 30% as compared to that using the conventional flip-flop.

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area- efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 m with under 1uW power consumption for providing 0.7degC effective resolution at 1 sample/sec processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.

Conditional-capture flip-flop technique for statistical power reduction

Conventional flip-flops such as hybrid latch-flip-flop (HLFF), semi-dynamic flip-flop (SDFF), and sense amplifier-based flip-flop (SAFF), which are the fastest, are inefficient as far as power consumption is concerned. This is because the internal nodes are repeatedly precharged and discharged at every clock cycle even when they are evaluating the same value. Hence, they consume a large amount of power regardless of input statistics. This flip-flop design technique eliminates unnecessary transitions to minimize power with no impact on speed.

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

A CMOS charge pump based on a transfer blocking technique and a modified precharge scheme is proposed for avoiding reversion loss and relaxing the timing restrictions imposed on input clocks. Comparison results in an 80-nm CMOS process indicate that, with no loading current, the output voltage of the proposed charge pump reaches almost 98% of the ideal boosting level with switching ripple reduced by up to 97%. They also indicate that output voltage deviations due to temperature and process variations are reduced by 24%-98% and 81%-95%, respectively.

45nm low-power embedded pseudo-SRAM with ECC-based auto-adjusted self-refresh scheme

In this paper, a low-power embedded pseudo-SRAM adopting novel auto-adjusted self-refresh control scheme has been designed. The proposed self-refresh control scheme automatically extends the self-refresh period by monitoring the number of failed cells using error correction code (ECC). The scheme can provide a substantial reduction of data-retention power consumption by choosing an optimal self-refresh period regardless of process, voltage, and temperature (PVT) variations. A 4-Mb embedded pseudo-SARM designed in a 45-nm embedded DRAM technology providing 1.1-V 166-MHz random cycle operation achieves 57-uW data retention power consumption at room temperature.

Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

This brief presents a pulsewidth modulation buck converter with an adaptive ramp amplitude control. The proposed buck converter can improve the load transient response and the reference tracking speed. A chip was fabricated in a 0.18-μm CMOS technology. Measurement results showed that the overshoot/undershoot at the output during the load transient period was reduced by up to 57% for a 450-mA load current step and that the reference tracking speed was improved by up to 71% for a 1.5-V output voltage change. The measured maximum power conversion efficiency was 92.6% at 3-MHz switching frequency when input and output voltages are 3.3 and 2 V, respectively.

Low-power class-AB CMOS OTA with high slew-rate

In this paper, a novel low-power class-AB CMOS OTA with high slew-rate is presented. The proposed OTA is based on class-AB input stage using a novel adaptive-biasing. The proposed OTA designed using a standard 0.18-um CMOS technology indicates that rising and falling slew-rates of +4.92 V/μS and −5.04 V/μS with worst-case settling time of 2.1 μS, a voltage gain of 48.97 dB with GBW of 57.27 kHz and phase margin of 78.18 degree were achieved with 10-pF load capacitance and 1.8-V supply voltage. The proposed OTA consumes an overall current of 1.09 μA, and occupies a silicon area of 0.008 mm2.

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18-mum CMOS technology. The experimental result indicates that the proposed synchronous counter achieves a power saving of 64% with 15% device count reduction.

Low-Voltage Bootstrapped CMOS Drivers With Efficient Conditional Bootstrapping

In this paper, a set of low-voltage bootstrapped CMOS drivers are presented to reduce power consumption and improve switching speed for driving a large capacitive load. The proposed drivers can reduce the power consumption by making bootstrap operations conditional to input statistics. They also improve switching speed by providing larger bootstrap voltages for the same amount of integrated bootstrap capacitance as compared with conventional bootstrapped drivers. The proposed drivers were designed using 0.18- CMOS technology. The comparison results indicate that the proposed drivers achieve power savings up to 97% with 13%-22% improvements on switching speed as compared with the conventional design.

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

A slew-rate-controlled output driver having a constant transition time irrespective of environmental variations is described in this brief. The proposed output driver employs a capacitive feedback between the output and input of the driver to allow its transition time independent of process, voltage, temperature and output load variations. The proposed output driver was designed and fabricated using a 0.13-mum CMOS process. According to our experimental results, the normalized variation on transition time of the proposed output driver due to PVT variations was improved by 74%-80% as compared to the conventional output driver. The comparison result also indicates that the normalized variation on transition time due to output load change from 10 to 100 pF (10 times variation) in typical process, voltage and temperature corners was improved by up to 66%.