Ching-Fang Huang

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission.

Package-strain-enhanced device and circuit performance

The hole mobility enhancement can be as high as /spl sim/18% for SiO/sub 2/ and /spl sim/20% for high-k HfO/sub 2/ gate stack dielectrics with the uniaxial compressive strain (0.2%) parallel to the channel. The highest drain current of /spl sim/22% at saturation and /spl sim/30% at linear region is observed for the bulk Si PMOS with high-k gate stacks. The drain current and hole mobility of bulk Si PMOS are degraded under the small biaxial tensile strain, while substrate-strained Si device displays the opposite. The nonoptimized ring oscillator has the speed enhancement of /spl sim/7% under the uniaxial tensile strain parallel to NMOS channel. Proper package strain also gives the drive-current as well as mobility enhancement at 100/spl deg/C.

Performance enhancement of ring oscillators and transimpedance amplifiers by package strain

The appropriate external stress can enhance a device and circuit performance. The 7.4% speed enhancement is achieved for the 250-nm node ring oscillator under uniaxial tensile strain for a mutually perpendicular layout of the NFET and the PFET. The speed enhancement is less than 1.5% for the conventional parallel layout of the NFET and the PFET. A 180-nm node transimpedance amplifier has a /spl sim/ 5% bandwidth enhancement using a biaxial tensile strain or a uniaxial tensile strain parallel to the NFET channel to tune the peaking frequency of active inductor in the circuit. The package strain can provide an extra useful parameter for the future digital and analog circuit design.

Dynamic Bias Instability of p-Channel Polycrystalline-Silicon Thin-Film Transistors Induced by Impact Ionization

The dynamic stress switching of p-channel polycrystalline-silicon (poly-Si) thin-film transistors from full depletion to accumulation bias creates the high electric field near source/drain (S/D) junctions due to the slow formation of the accumulated electrons at the SiO2/poly -Si interface. The high electric field causes impact ionization near the S/D, where the secondary electrons surmount the SiO2 barrier and are trapped near the interface. The channel region near the S/D is inverted to p-type by the trapped electrons, and the effective channel length is reduced. The drain current increases with the stress time, particularly for short-channel devices.

Effects of Applied Mechanical Uniaxial and Biaxial Tensile Strain on the Flatband Voltage of (001), (110), and (111) Metal–Oxide–Silicon Capacitors

The flatband-voltage shift of metal-oxide-silicon capacitors is investigated under the application of low-level stress (up to 220 MPa of biaxial stress and 380 MPa of uniaxial stress) to different substrate orientations. We propose that the flatband-voltage shift be modeled as the net effect of silicon-band-edge shifts and modulation of the separation between the band edge and the Fermi level under low levels of applied mechanical strain. For the (001) n-type substrate, a negative flatband-voltage shift is observed due mainly to the downward shift of the conduction-band edge, while a positive flatband-voltage shift is observed for the (001) p-type substrate due to the upward shift of the valence-band edge. For the uniaxial tensile strain on n-substrate capacitors for (110) and (111) substrates, the modulation of band-edge and Fermi-level separation by the conduction-band density of states exceeds the downward shift of the conduction band, which induces a positive flatband shift that is distinct from that observed in the (001) n-substrate. The shift of the band edges is determined by the proposed model and compared with theoretical calculations.

Dynamic bias temperature instability of p-channel polycrystalline silicon thin-film transistors

The impact ionization that occurred near channel-S/D junctions is responsible for the dynamic bias temperature instability (BTI) of p-channel poly-Si thin-film transistors (TFTs). Impact ionization is induced by lateral electric field when gate voltage switches from inversion or full-depletion to accumulation bias. Drain current increases initially due to shortened effective channel length. As the stress time increases, the grain barrier height increases to reduce the drain current, especially at high temperature. In addition to the transient switches, the plateau portions of the gate pulse have significant impact on the device degradation for large stress amplitudes.

Threshold Voltage and Mobility Extraction of NBTI Degradation of Poly-Si Thin-Film Transistors

The conventional continuous scan and Delay-ID, lin methods of negative bias temperature instability characterization are not applicable for polycrystalline silicon thin-film transistors due to significant recovery effect and mobility degradation, respectively. An improved on-the-fly (OTF) method is proposed to simultaneously extract the threshold voltage shift and mobility degradation. In addition, the improved OTF method is more accurate than the continuous scan due to less recovery effect. The exponents of reaction-diffusion mechanism can be clearly determined using the new method.

Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is ~107 s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration.