Jim-Shone Chen

15.4: Excellent Performance of Indium-Oxide-Based Thin-Film Transistors by DC Sputtering

Results on indium-oxide-based transparent oxide TFTs, which the active layer is prepared by DC sputtering, are presented. The fabricated TOS TFTs show high mobility (37 cm2/V-s), high ON/OFF current ratio and large on-state current. Fabricating oxide TFTs on temperature-sensitive substrates is also attainable owing to the low temperature process of the active layer preparation.

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler-Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.

Dynamic Bias Instability of p-Channel Polycrystalline-Silicon Thin-Film Transistors Induced by Impact Ionization

The dynamic stress switching of p-channel polycrystalline-silicon (poly-Si) thin-film transistors from full depletion to accumulation bias creates the high electric field near source/drain (S/D) junctions due to the slow formation of the accumulated electrons at the SiO2/poly -Si interface. The high electric field causes impact ionization near the S/D, where the secondary electrons surmount the SiO2 barrier and are trapped near the interface. The channel region near the S/D is inverted to p-type by the trapped electrons, and the effective channel length is reduced. The drain current increases with the stress time, particularly for short-channel devices.

Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation

This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under off -state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant on-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I- V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.

Dynamic bias temperature instability of p-channel polycrystalline silicon thin-film transistors

The impact ionization that occurred near channel-S/D junctions is responsible for the dynamic bias temperature instability (BTI) of p-channel poly-Si thin-film transistors (TFTs). Impact ionization is induced by lateral electric field when gate voltage switches from inversion or full-depletion to accumulation bias. Drain current increases initially due to shortened effective channel length. As the stress time increases, the grain barrier height increases to reduce the drain current, especially at high temperature. In addition to the transient switches, the plateau portions of the gate pulse have significant impact on the device degradation for large stress amplitudes.

Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress

This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

Comprehensive study of bias temperature instability on polycrystalline silicon thin-film transistors

The negative and positive bias temperature instabilities are investigated on p-channel and n-channel TFTs with four different combinations. The stress-induced hump in the subthreshold region is observed for PBTI on p-channel TFTs and NBTI on n-channel TFTs. The hump is attributed to the edge transistors along the channel width direction. Higher electric field at the corners induces more trapped carriers in the insulator as compared to channel transistor. In contrast, no humps are observed for NBTI on p-channel TFTs and PBTI on n-channel TFTs. For NBTI on p-channel TFTs, the interface traps are generated by breaking the Si-H bonds and are responsible for the negative ¿VT. On the other hand, electrons are trapped in the insulator and induce positive ¿VT for PBTI on n-channel TFTs.

Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is ~107 s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration.

P‐109: Drain Bias Effect on Characteristics of Reverse Sub‐threshold Region

We have investigated device characteristics utilizing top-gate structure to define the electric characteristics and qualities the value of drain-source current. At the same time, the device operation for high drain voltage mechanism was also investigated. The new terminal with positively top gate bias can significantly decrease the reverse sub-threshold leakage current more than one order and keep on 100% Ion improvement for high drain bias operation.

22.4: In‐Cell Multiple Ambient Light Sensor (ALSs) LCD Integration Using Si‐based Photonic Sensor by a‐Si TFT Technology

We have developed a new AMLCD with multiple ambient light sensors (ALSs) for reducing backlight (BL) power consumption, and false sensing of ambient illuminance. ALSs perform well in showing BL control for power-saving, even though one of the sensors is covered by a finger shadow. Architecture of integrated ALS with a-Si and LTPS technologies are presented. We fabricate the in-cell, and wide-dynamic-sensing ALSs display using new light sensor technology. Photo-electrical characteristics with well linearity and reliability under long-term operation were observed.