Hung-Chang Sun

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission.

Dynamic Bias Instability of p-Channel Polycrystalline-Silicon Thin-Film Transistors Induced by Impact Ionization

The dynamic stress switching of p-channel polycrystalline-silicon (poly-Si) thin-film transistors from full depletion to accumulation bias creates the high electric field near source/drain (S/D) junctions due to the slow formation of the accumulated electrons at the SiO2/poly -Si interface. The high electric field causes impact ionization near the S/D, where the secondary electrons surmount the SiO2 barrier and are trapped near the interface. The channel region near the S/D is inverted to p-type by the trapped electrons, and the effective channel length is reduced. The drain current increases with the stress time, particularly for short-channel devices.

Dynamic bias temperature instability of p-channel polycrystalline silicon thin-film transistors

The impact ionization that occurred near channel-S/D junctions is responsible for the dynamic bias temperature instability (BTI) of p-channel poly-Si thin-film transistors (TFTs). Impact ionization is induced by lateral electric field when gate voltage switches from inversion or full-depletion to accumulation bias. Drain current increases initially due to shortened effective channel length. As the stress time increases, the grain barrier height increases to reduce the drain current, especially at high temperature. In addition to the transient switches, the plateau portions of the gate pulse have significant impact on the device degradation for large stress amplitudes.

Enhanced recovery of light-induced degradation on the micromorph solar cells by electric field

The recovery of light-induced degradation of the tandem micromorph solar cell by applying reverse bias is compared with the single-junction amorphous silicon solar cell. The illuminated current density-voltage characteristics and external quantum efficiency show that the degradation of both the micromorph and the amorphous silicon cells can be recovered by applying sufficient reverse bias. The micromorph cell was recovered at smaller reverse bias than amorphous silicon cell. The abundant H in the microcrystalline silicon bottom cell of the micromorph cell can act as a reservoir to repair the defects in the amorphous silicon top cell at the reverse bias. This is responsible for small recovery bias of tandem cells.

Threshold Voltage and Mobility Extraction of NBTI Degradation of Poly-Si Thin-Film Transistors

The conventional continuous scan and Delay-ID, lin methods of negative bias temperature instability characterization are not applicable for polycrystalline silicon thin-film transistors due to significant recovery effect and mobility degradation, respectively. An improved on-the-fly (OTF) method is proposed to simultaneously extract the threshold voltage shift and mobility degradation. In addition, the improved OTF method is more accurate than the continuous scan due to less recovery effect. The exponents of reaction-diffusion mechanism can be clearly determined using the new method.

Comprehensive study of bias temperature instability on polycrystalline silicon thin-film transistors

The negative and positive bias temperature instabilities are investigated on p-channel and n-channel TFTs with four different combinations. The stress-induced hump in the subthreshold region is observed for PBTI on p-channel TFTs and NBTI on n-channel TFTs. The hump is attributed to the edge transistors along the channel width direction. Higher electric field at the corners induces more trapped carriers in the insulator as compared to channel transistor. In contrast, no humps are observed for NBTI on p-channel TFTs and PBTI on n-channel TFTs. For NBTI on p-channel TFTs, the interface traps are generated by breaking the Si-H bonds and are responsible for the negative ¿VT. On the other hand, electrons are trapped in the insulator and induce positive ¿VT for PBTI on n-channel TFTs.

EUV degradation of high performance Ge MOSFETs

High energy 13.5 nm EUV (~92 eV) induced Ge MOSFET degradation is reportedly for the first time. The degradation of threshold voltage, subthreshold swing, and channel mobility is attributed to the generation of interface traps and oxide fixed charges. Much more severe degradation of S.S. on nFETs as compared to pFETs suggests that acceptor type Dit in the upper half of Ge bandgap are generated by EUV radiation. ΔQit may originate from the dangling bonds at interface. Positive ΔQf is due to the fixed charges of oxygen vacancy. The generation of bulk defects in Ge increases the drain leakage current, leading to the reduction of current on/off ratio.

Radiation Impact of EUV on High-Performance Ge MOSFETs

High-energy extremely ultraviolet (EUV)-induced Ge MOSFETs degradation is investigated. The degradation of threshold voltage, subthreshold swing (SS), and channel mobility is attributed to the generation of interface traps and oxide fixed charges. Much more severe degradation of SS and VT on n-FETs compared to p-FETs suggests that more interface defects in the upper half of Ge bandgap are generated by EUV radiation than in the lower half bandgap. The increase of interface trap is responsible for the mobility degradation of n-FETs due to Coulomb scattering.

Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is ~107 s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration.

A design of 1T memory cells using channel traps for long data retention time

One-transistor (1T) memory cells with long data retention time is achieved with the modulation of drain current by channel traps. For simple demonstration, poly-Si TFTs are used, and grain boundary traps induced by excimer laser annealing are used as channel traps. The channel length in this work is 6 μm and the extrapolated data retention time can be as long as ~107 s at half of the current window. With the assumption that total number of traps is proportional to device volume and leakage current is proportional to the peripheral areas, retention time is scaled with gate length. For 30 nm devices, retention time is estimated to be ≥ 5×104 s. Compared with the conventional Zero-capacitor random access memory (Z-RAM), the channel trap memory provides better retention characteristics. For practical applications, the new channel trap cell has the same gate structure as logic devices, and can be potentially embedded in SoC platform. Due to the defect tolerance of cell channel and the low-temperature process, the 3D (multi-layer) memory structure by stacking the cells vertically can be potentially implemented more easily than flashtype devices [1]. In principle, the channel traps cells can also be implemented in bulk Si and the localized channel traps can be formed in the scaled devices using implantation techniques. This paper proposes a design of 1T memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.