Guang-Kaai Dehng

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS

In recent years, the increasing popularity of mobile devices, such as smart- phones and tablets, is driving the demand for integrating multiple radios on a single SoC to reduce cost, form factor and external BOM. These devices require ubiquitous wireless connectivity, which means concurrent operation with different radios. While concurrent operation of multiple radios brings excellent user experiences, there exist great challenges in dealing with radio co-existence in an SoC. For example, concurrent operation between WiFi and BT, both oper- ating in the 2.4GHz ISM band, sets additional requirements in RF front-end cir- cuits and system control. In addition, thermal effect of the integrated WiFi PA needs to be compensated to minimize its impact on the frequency-precise GPS system.

A 0.13

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1deg RMS phase error and the measured phase noise is -164.5 dBc/Hz at 20 MHz offset from a 914.8 MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/-12 dBm for the low bands (850/900 MHz) and 3 dB/-11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 mum CMOS technology and occupies 10.5 mm2. The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5 times 5 mm2 40-pin QFN package.

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A low-noise LC-tank VCO with a constant KVCO for GSM/GPRS/EDGE applications is presented. The proposed compensation technique helps to minimize the KVCO variation within the operation frequency of interest. This VCO is incorporated with a fractional-N frequency synthesizer and a DCT and is implemented in a 0.13 mum CMOS process. The measured KVCO is 29 MHz/V with a plusmn10% tuning range for a single sub-band and the overall KVCO variation is plusmn2.5% when the compensation technique is enabled. Based on this low-noise VCO, the achieved DCT phase noise is -165 dBc/Hz at a 20 MHz frequency offset from a 915 MHz carrier and a SAW-less DCT in the 2 G mobile application becomes feasible.

m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

A highly integrated ultra-low-cost high-performance Bluetooth 3.0+EDR SoC is implemented in 0.11-μm digital CMOS technology. The transceiver has an integrated balun shared between TX and RX, eliminating the need for a separate T/R switch. A 4 × LO-based VCO is implemented to reduce LO pulling and to minimize TX out-of-band spurious emissions. The transmitter provides high output power of +10 and +7 dBm in BDR and EDR3 modes respectively, with 1.5-kHz frequency stability and <; 6% rms DEVM. The receiver sensitivity is -95.5, - 96.5, and -89 dBm for BDR, EDR2, and EDR3 modes respectively. Total SoC DC current consumption for continuous TX transmission at +10 dBm output power is 48 mA and for continuous RX reception at reference sensitivity level is 35 mA. Total die size is 5.7 mm2, of which 1.8 mm2 is occupied by RF, analog, and PMU circuits.

A low-noise VCO with a constant K VCO for GSM/GPRS/EDGE applications

This paper presents an integrated 26-MHz digitally-controlled crystal oscillator (DCXO) with temperature compensation function for multi-standard cellular applications, that achieves a phase noise of -154 and -159 dBc/Hz at 10 kHz and 100 kHz offset, respectively. The frequency instability over temperature is compensated by built-in temperature sensor and compensating capacitor. The frequency instability from -10 to 55 degC is about +/- 1 ppm. The AFC frequency tuning is done by a digitally-controlled metal-oxide-metal capacitor array that is 13-bit thermometer decoded. The DCXO is implemented in a 0.13-mum CMOS technology.

An Ultra-Low-Cost High-Performance Bluetooth SoC in 0.11-

The growing demand for high-speed wireless communication has driven the evolution of cellular phone networks. New-generation cellular standards use wider channel bandwidth and more sophisticated modulation to obtain higher data-rates. Due to various cellular standards, chip providers are required to offer highly integrated solutions that support 2G, 3G, and even 4G in one chip. This paper presents a receiver supporting 2G quad bands and 3G TD-SCDMA dual bands. Figure 20.7.1 shows the 2G/3G receiver, whose front-end current-mode outputs are combined at baseband CR filter and biquad PGA, which are shared between all bands. A dynamic gain-bandwidth-product-extension circuit technique is used to remove a transimpedance amplifier to save die area and current.

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A low-noise EDGE transmitter implemented in a 65nm CMOS process using direct-conversion architecture for low-band application is presented. The transmitter consists of a programmable-gain I/Q modulator, a frequency divider and a power detector for carrier leakage calibration. The design delivers maximum output power ≫ 1.5 dBm with a 0.5 dB gain step for the 30 dB dynamic range and has ≪ −68 dBc modulation spectrum at 400-kHz offset under maximum gain level. The out-of-band noise at 20 MHz offset with the power amplifier is −80.9 dBm with 100-kHz resolution bandwidth. The carrier leakage suppression after calibration can reach −50 dBc. The design consumes 21 mA at 1.5-V supply and 40 mA at 2.7-V supply and is housed in a 40-pin QFN package.

CMOS

An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.

A temperature-compensated low-noise digitally-controlled crystal oscillator for multi-standard applications

A highly-integrated, ultra-low-cost Bluetooth SOC implemented in 0.11μm digital CMOS technology is disclosed. To reduce BOM count and cost, an integrated balun is designed for the transceiver front-end. A 4xLO based VCO is implemented to reduce LO pulling, and minimize TX out-of-band spurious in the direct-conversion transmitter. The transmitter provides high output power at +10dBm and +7dBm in BDR and EDR3 modes respectively, with 1.5-kHz frequency stability and <6% RMS DEVM The receiver sensitivity is better than −95.5dBm, −96.5dBm and −89dBm for BDR, EDR2 and EDR3 modes respectively. DC current consumption for continuous TX transmission at +10dBm output power is 48mA, and for continuous RX reception at reference sensitivity level is 35mA. Total die size is 5.7mm2, of which 1.8mm2 is occupied by RF, analog and PMU circuits.

20.7 A multi-band inductor-less SAW-less 2G/3G-TD-SCDMA cellular receiver in 40nm CMOS

The RF front-end complexity in 4G multimode multiband cellular radios has increased dramatically, requiring integration of PAs, filters and switches in a single module to reduce the RF footprint. This paper presents a fully integrated multimode TDD transmit front-end module (TXM) supporting GSM/EDGE/TD-SCDMA/TD-LTE in multiple bands. The TXM is implemented with three die on a 2-layer laminate LGA module (Figs. 13.1.1 and 13.1.7). Two multimode multiband power amplifier paths (LB/HB) are implemented in a 0.153µm 1P6M CMOS process, followed by power combiners and harmonic filters in a 0.18µm 3M2V IPD die and finally an SP10T antenna switch in a 0.18µm 1P3M SOI process. The Si substrate of good thermal conductivity dissipates the heat generated by PA transistors to the laminated substrate, which solder mask opened and lots of ground vias are deployed underneath the die to effectively conduct the heat out of the package.