Chingwei Yeh

Layout techniques supporting the use of dual supply voltages for cell-based designs

Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous researches focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this paper, we present layout techniques that make the approach feasible in a cell-based design environment. A new block layout style is proposed to support the voltage scaling with conventional standard cell libraries. The block layout can be automatically generated via a simulated annealing based placement algorithm. In addition, we propose a new cell layout style with built-in multiple supply rails. Using the cell layout, gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques produce very promising results.

Timing driven power gating

Power gating is effective for reducing leakage power. Previously, a distributed sleep transistor network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the maximum instantaneous current (MIC) through sleep transistors. In this paper, we propose a new methodology for determining the size of sleep transistors for the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop. We also present efficient heurists for minimizing the sizes of sleep transistors. Our experimental results are very exciting

High-Speed and Low-Power Design Techniques for TCAM Macros

Ternary content addressable memory (TCAM) is an important component for many applications. For TCAM-based networking systems, the rapidly growing size of routing tables brings with it the challenge to design higher search speeds and lower power consumption. In this work, two techniques are proposed to realize high-performance and low-power TCAM for IP address lookup. One technique is the tree AND-type match-line scheme for high search speed. The other technique is the segmented search-line scheme for low power. The implemented 1.8 V 0.18 mum 256 times 128b TCAM macro achieves a 1.56 ns search time using a 1.42 fJ/bit/search of energy.

An AND-type match-line scheme for high-performance energy-efficient content addressable memories

High search speed and low energy per search are two major design goals of content-addressable memories (CAMs). In this paper, an AND-type match-line scheme is proposed to realize a high-performance energy-efficient CAM. The realized 256 /spl times/ 128-b CAM macro, based on a 0.18-/spl mu/m 1.8-V CMOS process, achieves a 2.1-ns search time. When both the stored and search data are generated from an on-chip 4 /spl times/ 32-b LFSR with the same seed, the measured energy is 2.33-fJ/bit/search.High search speed and low energy per search are two major design goals of content-addressable memories (CAMs). In this paper, an AND-type match-line scheme is proposed to realize a high-performance energy-efficient CAM. The realized 256 /spl times/ 128-b CAM macro, based on a 0.18-/spl mu/m 1.8-V CMOS process, achieves a 2.1-ns search time. When both the stored and search data are generated from an on-chip 4 /spl times/ 32-b LFSR with the same seed, the measured energy is 2.33-fJ/bit/search.

Gate-level design exploiting dual supply voltages for power-driven applications

The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. We first use a maximum-weighted independent set formulation for voltage reduction on non-critical parts of the circuit. Then, we use a minimum-weighted separator set formulation to do gate sizing and integrate the sizing procedure with a voltage scaling procedure to enhance power saving on the whole circuit. The proposed methods are evaluated using the MCNC benchmark circuits. An average of 19.12% power reduction over the circuits having only one supply voltage has been achieved.

An AND-type match-line scheme for energy-efficient content addressable memories

An AND-type match-line scheme is fabricated in a 0.18 /spl mu/m 1.8V CMOS process. The 256/spl times/128b CAM achieves a faster search time and a 20% energy reduction compared with NOR designs. This AND-type circuit has a search time of 1.75ns with an energy of 0.57fJ/bit/search.

Fast and compact dynamic ripple carry adder design

Adders are fundamental building blocks and often constitute part of the critical path. In this paper, we propose four high-speed ripple carry adder designs using dynamic circuit techniques. CMOS technology based SPICE simulations show that the proposed dynamic ripple carry adders are at least two times faster than the conventional static ripple carry adder. Further, all of the proposed designs compare much favorably to a previous dynamic ripple carry adder design that employs DCVS (differential cascode voltage switch) logic.

Optimization by iterative improvement: an experimental evaluation on two-way partitioning

Recently, Johnson et al. [1989] presented an excellent comparison of simulated annealing and Kernighan-Lin algorithms. However, their test beds were limited to random and geometric graphs. We present a complete evaluation by adding real circuitry into the test beds. A two-level partitioning algorithm called the primal-dual algorithm is also incorporated for comparison. We show that at least 500 runs are necessary to demonstrate the performance of the Fiduccia-Mattheyses algorithm, whereas traditional way of evaluation tends to underestimate. Nevertheless, our new results show that for two-way partitioning on real circuits, the primal-dual algorithm is, in general, a better choice than both the Fiduccia-Mattheyses algorithm and the simulated annealing algorithm. This conclusion is more likely to hold when the primal-dual algorithm is switched to a simpler mode. >

Design of standard cells used in low-power ASIC's exploiting the multiple-supply-voltage scheme

ASIC design utilizing the multiple-supply-voltage (MSV) scheme has been shown to be efficient in reducing the power consumption. A new layout style of standard cells to be used in ASIC designs is proposed to effectively exploit the advantages afforded by the MSV scheme. Each standard cell is designed to use two power rails that are fed with different supply voltages. Then, the cells can be butted together arbitrarily no matter whether the cells are supplied from a high or low voltage, and the existing P&R tool can place and route the circuit as usual. As compared to the design with only one supply voltage, the average saving of power consumption of the new design (using the new cells and adopting the MSV scheme) is over 30%, but the average area overhead is only about 8%. Meanwhile, the average interconnection length is only increased by about 7.5%.

TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines

Tree-style AND-type match-line and segmented search-line schemes cooperatively improve TCAM speed and energy efficiency for applications like IP-address lookup in a network router. Fabricated in a 0.13mum process, the TCAM achieves 1.10ns search time with 0.348 fJ/b/search