Chung-Hsun Huang

Design of a Low-Voltage Low-Dropout Regulator

A low-voltage low-dropout (LDO) regulator that converts an input of 1 V to an output of 0.85-0.5 V, with 90-nm CMOS technology is proposed. A simple symmetric operational transconductance amplifier is used as the error amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO regulator. In the rail-to-rail output stage of the EA, a power noise cancellation mechanism is formed, minimizing the size of the power MOS transistor. Furthermore, a fast responding transient accelerator is designed through the reuse of parts of the EA. These advantages allow the proposed LDO regulator to operate over a wide range of operating conditions while achieving 99.94% current efficiency, a 28-mV output variation for a 0-100 mA load transient, and a power supply rejection of roughly 50 dB over 0-100 kHz. The area of the proposed LDO regulator is only 0.0041 mm2, because of the compact architecture.

Fast and compact dynamic ripple carry adder design

Adders are fundamental building blocks and often constitute part of the critical path. In this paper, we propose four high-speed ripple carry adder designs using dynamic circuit techniques. CMOS technology based SPICE simulations show that the proposed dynamic ripple carry adders are at least two times faster than the conventional static ripple carry adder. Further, all of the proposed designs compare much favorably to a previous dynamic ripple carry adder design that employs DCVS (differential cascode voltage switch) logic.

The CMOS carry-forward adders

The ripple-carry adder (RCA) has the simplest circuit structure but the longest delay among all adders. Thus, it is often realized with the dynamic circuits when speed is the major concern. In this paper, we propose circuit-level and architecture-level innovations over the dynamic RCA (DRCA) that lead to high operation speed and low hardware overhead. Circuit-wise, we propose a cost-effective way to eliminate the race problem of DRCA. Architecture-wise, we propose a new carry-forwarding scheme that combines a diagonal forwarding with the multilevel folding for dramatic speed improvement of the DRCA. Finally, a new multilevel carry-forwarding scheme is proposed to reduce the circuit complexity while keeping the speed. Based on all the proposed techniques, a 32-bit dynamic carry-forward adder (CFA32) with two-level carry forwarding is designed and fabricated with the 0.25-/spl mu/m CMOS technology. The CFA32 consists of 1202 MOS transistors, and occupies only 0.017-mm/sup 2/ silicon area after layout. The measurement result, which agrees with the simulation result, shows that the adder needs only 640 ps to perform an add operation under room temperature. Using the same techniques, a 64-bit carry-forward adder (CFA64) with two-level forwarding technique is also designed and simulated. The CFA64 consists of only 2502 MOS transistors, and the simulation result shows the evaluation time is only 780 ps.

A fast and high efficiency buck converter with Switch-On-Demand Modulator for wide load range applications

This paper presents a buck converter with a switch-on-demand modulator (SOM) for achieving a fast transient response, small voltage ripple, and high power efficiency over a wide load range. Switching power MOS on or off depending on the energy demand of the load circuit results in a hybrid operation of pulse width modulation (PWM) and pulse frequency modulation (PFM). The proposed buck converter uses 90nm CMOS process and can achieve a transient response time of less than 2µs and a voltage ripple of 18mV at a load current range of 10mA∼500mA with a power efficiency above 88%.

A fast wake-up power gating technique with inducing a balanced rush current

Power gating technique is important for saving the leakage power, especially for the very deep-submicron system-on-a-chip designs. Although the multi-threshold voltage CMOS (MTCMOS) technology can enable us to cut down the leaky path easily, the induced power/ground bounce is getting worse and can not wake up from power down mode quickly. In this paper, we propose a new concept of power gating technique by balancing the variations of rush current to accelerate the wake-up procedure for a given power/ground bounce specification. Performance evaluations of a 40-bit ALU circuit using the TSMC 0.18μm CMOS technology show that our proposed power gating technique can achieve a 10.23% reduction in wake-up time while keeping the power bounce specification, as compared with the conventional power gating technique.

A low complexity edge-preserved image compression algorithm for LCD overdrive

Overdrive technique is mandatory for liquid crystal display (LCD) to mitigate the motion blur phenomenon. As the display resolution increases, the image data should be highly compressed to reduce the usages of frame memory and bandwidth. Since current high quality compression algorithms inevitably require large embedded memory (line buffer) and complex computations, a low complexity line-buffer-free edge-preserved compression algorithm is proposed in this paper to reserve the edge information for overdrive technique of LCD. Performance evaluations show that the proposed edge-preserved compression achieves above 20% PSNR improvements as compared to the conventional DPCM compression up to 6:1 compression ratio.

Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET)

Presents a slide covering the following: low power fixed-latency DSP accelerator; autonomous minimum energy tracking; adaptive voltage scaling; and intelligent voltage generation.

A compact programmable LDO regulator for ultra-low voltage SoC

This paper proposes a compact programmable low dropout (LDO) regulator for an ultra-low voltage system-on-a-chip (SoC) using the voltage scaling technique. Two innovative design concepts were proposed: a programmable multi-level resistor array that can precisely tune the ratio of the feedback resistor divider; and a current limiter that limits a small static current flowing through the resistor network while reducing the occupied area. Experimental results show that the monotonic 50-step programmable output ranging from 0.3V to 0.8V is achieved, with an input of 1V and a maximum load current of 100mA. The occupied area is only 0.017mm2.

A low-voltage high PSR LDO regulator with a simple ripple cancellation technique

This paper presents a low-voltage low-dropout voltage (LDO) regulator achieving a high power supply rejection (PSR) performance over a wide frequency range. A simple PSR enhancing circuit (PSRE) establishing a power noise (ripple) cancellation mechanism to avoid power noise passing through the power MOS transistor. A LDO regulator adopting the proposed PSRE was designed using a 1-V 90 nm CMOS process to convert an input of 1.2V–0.8V to an output of 0.85V–0.5V at a load current range of 0–100 mA. Post-layout simulations show that a PSR is above −57 dB at 1MHz while the output spike during a 0.1mA–100mA load transient test is only 14mV.

A high throughput ASIC design for IPv6 routing lookup system

This paper presents a cache-centric, hash-based architecture within a application specific integrated circuit (ASIC) implementation for IPv6 routing lookup system. In ASIC, the binary content addressable memory (BCAM) as cache memory has a hit ratio of up to 80% with a FIFO replacement algorithm. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The results of postlayout simulations show that the ASIC operates in 3.6ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100 Gbps networks. The routing table only needs 10.24KB on-chip BCAM, 20.04KB offchip TCAM and 29.29MB DRAM for 3.6M routing entries in the proposed system.