Chiou-Yng Lee

Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields

For cryptographic algorithms, such as elliptic curve digital signature algorithm (ECDSA) and pairing algorithm, the crypto-processors are required to perform large number of additions and multiplications over finite fields of large orders. To have a balanced trade-off between space complexity and time complexity, in this paper, novel digit-serial and digit-parallel systolic structures are presented for computing multiplication over GF(2m). Based on novel decomposition algorithm, we have derived an efficient digit-serial systolic architecture, which involves latency of O(√{m/d}) clock cycles, while the existing digit-serial systolic multipliers involve at least O(m/d) latency for digit-size d. The proposed digit-serial design could be used for AESP-based fields with the same digit-size as the case of trinomial-based fields with a small increase in area. We have also proposed digit-parallel systolic architecture employing n-term Karatsuba-like method, where the latency can be reduced from O(√{m/d}) to O(√{m/nd}). This feature would be a major advantage for implementing multiplication for the fields of large orders. From synthesis results, it is shown that the proposed architectures have significantly lower time complexity, lower area-delay product, and higher bit-throughput than the existing digit-serial multipliers.

Digit-Serial Gaussian Normal Basis Multiplier over GF(2m) Using Toeplitz Matrix-Approach

This paper presents a novel algorithm for type-t Gaussian normal basis (GNB) binary finite field multiplication using Toeplitz matrix-vector representation. It is shown that the GNB multiplication can be realized through block Toeplitz matrix-vector-products. A digit-serial systolic GNB multiplier is proposed where each processing element is comprised of a Toeplitz multiplier and three registers. Analytical results indicate that our proposed architecture has significantly lower area complexity than existing digit-serial multipliers.

Scalable serial-parallel multiplier over GF(2 m ) by hierarchical pre-reduction and input decomposition

This paper presents a novel serial-parallel architecture for finite field multiplications over GF(2m) defined by irreducible trinomials as field polynomials. By recursive decomposition of one of the operands, and hierarchical pre-reduction of the other, it is possible to feed multiple bits in parallel to the serial-parallel structure. The level of parallelism could be doubled after each level of decomposition of the input operand, when high throughput rate is required. One of the key features of the proposed design is that its clock-period remains invariant with the digit-size. The area-complexity of the proposed design increases linearly with the digit-size, which is unlike some of the existing architectures, where area-complexity increases quadratically with the digit-size. Although the proposed structure involves more area compared with some of the existing architectures, since the clock-period of the proposed design is small, it involves significantly less area-delay complexity than the others.

Low-Complexity Digit-Serial Multiplier Over

In this paper, we have shown that a regular Toeplitz matrix-vector product (TMVP) can be transformed into a Toeplitz block TMVP (TBTMVP) using a suitable permutation matrix. Based on the TBTMVP representation, we have proposed a new

GF(2^{m})

(a,b)

Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition

-way TBTMVP decomposition algorithm for implementing a digit-serial multiplication. Moreover, it is shown that, based on iterative block recombination, we can improve the space complexity of the proposed TBTMVP decomposition. From the synthesis results, we have shown that the proposed TBTMVP-based multiplier involves less area, less area-delay product, and higher throughput compared with the existing digit-serial multipliers.

New digit-serial three-operand multiplier over binary extension fields for high-performance applications

Digit-serial polynomial basis multipliers over GF(2m) are broadly applied in elliptic curve cryptography, because squaring and polynomial reduction in GF(2m) are simple operations. In this paper, we define a partial product formula to derive a new digit-serial three-operand multiplication algorithm. On the basis of the proposed algorithm, we have derived a new digit-serial structures for computing three-operand multiplication. Our proposed structures can reduce latency (clock cycles) by approximately 50% compared to the existing digit-serial two-operand multipliers used to perform three-operand multiplication. Therefore, the proposed structure can achieve high-throughput designs. According to the analysis reports, the advantages of the proposed designs are a short critical path, a low area-delay product, and a high throughput.

Problems on Gaussian Normal Basis Multiplication for Elliptic Curve Cryptosystem

Several standards such as IEEE Standard 1363-2000 and FIPS 186-2 employ Gaussian normal basis (GNB). Gaussian normal basis is a special class of normal basis. Gaussian normal basis can solve the problem that multiplication in normal basis is an very difficult and complicated operation. Two equations have been proposed in the literature to transfer GNB to polynomial basis for easy multiplication. However, we find that GNB is not correctly transformed to polynomial basis for some m values over \(GF(2^{m})\). We will show the problems and expect some feedback about this problem from other researchers.

Fault Tolerant Dual Basis Multiplier Over GF (2m)

To fight against fault based side-channel cryptanalysis, a bit-parallel systolic dual basis multiplier using a time redundancy scheme is presented. This scheme is based on the extended dual multiplication to achieve the concurrent error correction (CEC) in the results. Analytical results reveal that our proposed CEC multiplier demands 1.87% space overheads, while the existing multipliers using parity prediction and time/hardware redundancy schemes demand at least 45% space overheads. Moreover, the time overhead of the proposed scheme amounts to only two clock cycles.

Efficient Bit-Parallel Multipliers in Composite Fields

Hardware implementation of multiplication in finite field GF(2^m) based on sparse polynomials is found to be advantageous in terms of space-complexity as well as the time-complexity. In order to design multipliers for the composite fields, we have found another permutation polynomial to convert irreducible polynomials into like-trinomials of the forms (x² + x + 1)^m + (x² + x + 1)ⁿ + 1, (x² + x)^m + (x² + x)ⁿ + 1 and (x⁴ + x + 1)^m + (x⁴ + x + 1)ⁿ + 1. The proposed bit-parallel multiplier over GF(2^4m) is found to offer a saving of about 33% multiplications and 42.8% additions over the corresponding existing architectures.