Chiradeep Mukherjee

Layered T full adder using Quantum-dot Cellular Automata

Fast changing world has driven technology towards a milestone where emerging technology like quantum-dot cellular automata (QCA) excels in terms of ultra-high packing density and extremely low power consumption. Quantum Cellular Automata has several deduction methodologies like Majority Voter, Universal QCA logic, FNZ logic & And-Or-Invert (AOI) logic none of which explores universal NAND-NOR based design in Boolean reduction techniques. This work proposes Layered T full adder with its basic primitive which works on the basis of universal NAND and NOR logic. Layered T gate is verified taking Coulombs law as the physics behind it. Layered T Gate is also used to implement full adder as primitive in processor based design which gives the best result in terms of cell requirement and area compared to the latest design.

Decoder segment optimization of ROM design in quantum dot cellular automata

Emerging technology proves its superiority through quantum dot cellular automata where confinements of electrons occur from all three dimensions. Effective area optimization in quantum dot cellular automata plays a pivotal role in memory designing. In the design of Read Only Memory(ROM), decoding section decides where specific information will be stored. Optimal design of decoder segment signifies the improved memory design. This paper introduces a new design of 4 bit row/column decoder in the ROM design. Designed decoder shows 25.89% reduction of effective area than the latest design proposed by Rigui Zhou et al at the cost of only four majority voter blocks.

Effect of temperature and kink energy in multilevel digital circuit using Quantum dot cellular automata

Quantum-dot Cellular Automata (QCA) is a paradigm for low power, high speed computation technique in the field of nanoscience. Till today three types of QCA structures are discussed among them magnetic and molecular QCA operates at room temperature but the metallic dot QCA structure operates at a very low temperature at around absolute zero degree Kelvin. In this paper we comprehended that if the spacing between two consecutive cells in a metallic dot QCA is reduced lower than 2nm then the operating temperature can be enhanced up to 12 degree Kelvin. Instead of using only one majority gate we have used multi-input level shifter circuit where four majority gates are used and the output depend on all the inputs and the majority gates operation. According to QCADesigner tool, 2nm spacing between two consecutive cell is taken as standard for any circuit. Multi input level shifter circuit based on Quantum-dot Cellular Automata (QCA) is working at increased temperature with decreasing cell space.

T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata

Quantum Dot Cellular Automata (QCA) plays a pivotal role in the emerging field of Nano electronics as well as in digital finite state machine design arena. Several gates and their proposals exist in this field all of which are recognized for their own characteristics. Majority voter is one of the several schemes of QCA. In this paper, a new gate termed as T-gate is proposed which is validated by thirteen standard functions and two input multiplexer circuit which reflects the reduction in the effective area as compared to the realization of the same by earlier methods. The T-gate can function as a universal logic gate and also as an inverter which can be realized by using fewer numbers of cells. T-gate implementation of 2×1 Multiplexer require no wire crossings and shows noticeable reduction in the cell count.

Majority-layered T hybridization using quantum-dot cellular automata

Abstract The atomistic quantum-dot cellular automata (QCA) based implementations of the reversible circuits have got tremendous exposures in the last few days, due to “room-temperature workability” of the QCA. The researchers are in serious need of a methodology that can realize the area-efficient QCA counterparts of reversible benchmark circuits. In this work, a novel methodology named majority-layered T hybridization is proposed to synthesize the reversible circuits using QCA. Firstly the reversible library consisting of CNTS Gates have been generated to validate the usability of the proposed methodology. Then, an elementary QCA module of 3×3 Toffoli Gate have been proposed and extended in the realization of 4×4, 5×5 and 6×6 Toffoli Gates (multi-control Toffoli Gates). The proper mathematical modelling of the several QCA design metrics like effective area, delay and O-cost has been established. The QCA counterpart of 3×3 Toffoli Gate reports 18.61% less effective area and 8.33% less O-cost compared to the previous Toffoli Gate designs. Moreover, the QCA layout of rd-32 reversible benchmark using multi-control Toffoli Gate has been employed to verify the scalability and reproducibility of the proposed methodology. The QCA layouts are generated, tested and simulated by renowned computer aided design tool QCADesigner 2.0.3.

Layered T comparator design using quantum-dot cellular automata

Comparator is crucial block in Central Processing Unit especially in the process of “Data Searching-Sorting” where huge amount of data needs to be searched during the Database Management operations. In this work, the logic design of 1-bit Quantum Cellular Automata (QCA) comparator has been proposed using the Layered-T AND and OR Gates. The proposed comparator layout needs 9.02% less effective area compared to the best reported design so far. The effect of cell misplacements on the proposed layout is thoroughly investigated. Moreover, the other QCA design metrics such as O-Cost, CostI are calculated for the proposed 1-bit Layered T Comparator circuit. The functionality of the proposed circuit is verified by computer aided design tool QCADesigner 2.0.3.

A Review Report on Solar Cell: Past Scenario, Recent Quantum Dot Solar Cell and Future Trends

Solar cell is the most promising renewable energy source in this modern era which converts light energy into electric energy. The solar cell has achieved a sharp growth as sustainable energy source in recent years. Solar cells can easily replace the fossil fuels as it is pollution free. The solar cell technology is also changing to find a new horizon. In this paper, the review of solar cell technology, starting from crystalline silicon solar cell to recent quantum dot solar cell is discussed. This paper also focused on the future trends of solar cells and its aspects.

Search of appropriate semiconductor for PIN Diode fabrication in terms of resistance analysis

The PIN diode is a promising device in the field of power electronics due to its lower reverse leakage current and lower capacitance. Power electronics industry searches suitable semiconductors as conventional silicon saturates in context of impedance performances with a specified device configuration in the analysis of PIN diode. This paper considers the different materials like Si, Ge, GaAs, SiC-3C, SiC-4H, SiC-6H, GaN-wZ, GaN-zB, InAs to study the variation of intrinsic resistance, junction resistance and total resistance with respect to forward current as well as to study these same parameters with respect to width of the intrinsic region. The characteristics of intrinsic, junction and total resistances of PIN diodes with 10mA forward bias current and 50 micron width of the intrinsic region are noted. Finally it concludes and proposes the superior semiconductor material for PIN diode.

Implementation of Toffoli Gate Using LTEx Module of Quantum-Dot Cellular Automata

Reversible logic design using Quantum Cellular Automata (QCA) is considered as a promising area in nanotechnology. Previously designed QCA layouts of the reversible gates have generally been designed in single layer except for the interconnections where multilevel wire crossing was used. In this paper the concept of multilayer based Layered T Exclusive OR module, namely LTEx module is proposed to design 3 × 3 Toffoli Gate. A comparison has made with the existing designs of Toffoli Gate and the result is showcasing that the circuits designed in the proposed methodology are more efficient in terms of effective area, O-Cost and input to output delay of the circuit. Moreover, the 3 × 3 Toffoli gate is designed with the scope for multi-control Toffoli gate to make reversible circuit design compact.

FPGA based effecient architecture for conversion of binay to residue number system

Today the most interesting research topic in theoretical point of view is Residue Number System (RNS). Its significance originates from the lack of carry propagation between its arithmetic units. To implement any modular process, the important step is the conversion from a residue number system (RNS) to binary. In modern telecommunication system and multimedia applications, the use of RNS increases day by day due to its many advantages such as low power consumption, high speed, very precise etc. Usually the translation of the output from residue to binary is the vital point in successful realizations of application specific architectures based on residual arithmetic. In this paper a novel architecture of parallel forward conversion (Residue to Binary number system) for signed number has been proposed successfully. This article also highlighted the mapping of this projected architecture on FPGA and shown it is very efficient on FPGA technology.