Saradindu Panda

T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata

Quantum Dot Cellular Automata (QCA) plays a pivotal role in the emerging field of Nano electronics as well as in digital finite state machine design arena. Several gates and their proposals exist in this field all of which are recognized for their own characteristics. Majority voter is one of the several schemes of QCA. In this paper, a new gate termed as T-gate is proposed which is validated by thirteen standard functions and two input multiplexer circuit which reflects the reduction in the effective area as compared to the realization of the same by earlier methods. The T-gate can function as a universal logic gate and also as an inverter which can be realized by using fewer numbers of cells. T-gate implementation of 2×1 Multiplexer require no wire crossings and shows noticeable reduction in the cell count.

Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra

Digital signal processing (DSP) operations are very important part of engineering as well as medical discipline. Designing of DSP operations have many approaches. For the designing of DSP operations, multiplication plays a important role to perform signal processing operations such as convolution and correlation. The aim of this paper is to design a multiplier circuit based on Vedic sutras and method for DSP operations based on ancient Vedic mathematics is contemplated. In this paper, we have given the design up to multipliers based on Vedic multiplication sutra ‘Urdhva-Tiryakbhyam’ the design of 4 × 4 has been sketched in DSCH2 and all the outputs have been given. The layout of those circuits has also been generated by Microwind. The internal circuit diagram of all the blocks has been explained. The noise power have been calculated by T-Spice-13 in 45 nm Technology. This algorithm is implemented in MATLAB and also compared with the inbuilt functions in MATLAB.

Majority-layered T hybridization using quantum-dot cellular automata

Abstract The atomistic quantum-dot cellular automata (QCA) based implementations of the reversible circuits have got tremendous exposures in the last few days, due to “room-temperature workability” of the QCA. The researchers are in serious need of a methodology that can realize the area-efficient QCA counterparts of reversible benchmark circuits. In this work, a novel methodology named majority-layered T hybridization is proposed to synthesize the reversible circuits using QCA. Firstly the reversible library consisting of CNTS Gates have been generated to validate the usability of the proposed methodology. Then, an elementary QCA module of 3×3 Toffoli Gate have been proposed and extended in the realization of 4×4, 5×5 and 6×6 Toffoli Gates (multi-control Toffoli Gates). The proper mathematical modelling of the several QCA design metrics like effective area, delay and O-cost has been established. The QCA counterpart of 3×3 Toffoli Gate reports 18.61% less effective area and 8.33% less O-cost compared to the previous Toffoli Gate designs. Moreover, the QCA layout of rd-32 reversible benchmark using multi-control Toffoli Gate has been employed to verify the scalability and reproducibility of the proposed methodology. The QCA layouts are generated, tested and simulated by renowned computer aided design tool QCADesigner 2.0.3.

Layered T comparator design using quantum-dot cellular automata

Comparator is crucial block in Central Processing Unit especially in the process of “Data Searching-Sorting” where huge amount of data needs to be searched during the Database Management operations. In this work, the logic design of 1-bit Quantum Cellular Automata (QCA) comparator has been proposed using the Layered-T AND and OR Gates. The proposed comparator layout needs 9.02% less effective area compared to the best reported design so far. The effect of cell misplacements on the proposed layout is thoroughly investigated. Moreover, the other QCA design metrics such as O-Cost, CostI are calculated for the proposed 1-bit Layered T Comparator circuit. The functionality of the proposed circuit is verified by computer aided design tool QCADesigner 2.0.3.

Search of appropriate semiconductor for PIN Diode fabrication in terms of resistance analysis

The PIN diode is a promising device in the field of power electronics due to its lower reverse leakage current and lower capacitance. Power electronics industry searches suitable semiconductors as conventional silicon saturates in context of impedance performances with a specified device configuration in the analysis of PIN diode. This paper considers the different materials like Si, Ge, GaAs, SiC-3C, SiC-4H, SiC-6H, GaN-wZ, GaN-zB, InAs to study the variation of intrinsic resistance, junction resistance and total resistance with respect to forward current as well as to study these same parameters with respect to width of the intrinsic region. The characteristics of intrinsic, junction and total resistances of PIN diodes with 10mA forward bias current and 50 micron width of the intrinsic region are noted. Finally it concludes and proposes the superior semiconductor material for PIN diode.

Implementation of Toffoli Gate Using LTEx Module of Quantum-Dot Cellular Automata

Reversible logic design using Quantum Cellular Automata (QCA) is considered as a promising area in nanotechnology. Previously designed QCA layouts of the reversible gates have generally been designed in single layer except for the interconnections where multilevel wire crossing was used. In this paper the concept of multilayer based Layered T Exclusive OR module, namely LTEx module is proposed to design 3 × 3 Toffoli Gate. A comparison has made with the existing designs of Toffoli Gate and the result is showcasing that the circuits designed in the proposed methodology are more efficient in terms of effective area, O-Cost and input to output delay of the circuit. Moreover, the 3 × 3 Toffoli gate is designed with the scope for multi-control Toffoli gate to make reversible circuit design compact.

Study on Localized Surface Plasmon to Improve Photonic Extinction in Solar Cell

Recently, plasmonic is given very much interest in analysis as a likely to manner to improvement in photonic extinction in solar cell structure. Its main expose is to concentrate and enhance the optical field due to strong interaction in plasmonic nanostructure that manipulates and concentrate photonic propagation at nano-dimension length scales. When light incident on the surface of plasmonic nanostructures it can excite mostly the valence electron gas which oscillates at the plasmonic frequency. In this paper, we have modeled finite-difference time domain based analysis for plasmonic nanostructure for manipulating various plasmonic field components with eigenvalue and characterized optical improvement including photonic absorption and scattering cross sections as well as extinction in plasmonic thin-film solar cell.

Performance Evaluation of Digital Comparator Using Different Logic Styles

Abstract In the present scenario, low power, speed, and size play a significant role specifically in the field of digital VLSI circuits. The major goal of this paper is to design and implement a digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. The results of this paper are simulated on the EDA tanner tool realized in 45-nanometer technology at 0.7 v supply voltage.

Effect of Surface Plasmon-Based Improvement in Optical Absorption in Plasmonic Solar Cell

In the last few years, plasmonics has attracted much attention and has been included in the principal domains of nanophotonics that can manage optical fields at the nanodimension level. Its exquisi...

Design of low power 12-bit magnitude comparator

In the advanced technology low power, speed and size play a significant role specifically in the field of magnitude VLSI circuits. In this paper small power dissipation and less area over conventional 2-bit comparator is proposed and using this comparator a new style 12-bit comparator is proposed. The main objective of this paper is to design and implement of magnitude comparator using different logic techniques and compared in terms of power consumption, propagation delay and transistor count. The results of this paper are simulated on the EDA tanner tool realized in 45-nanometer technology at 0.7v supply voltage.