Chong-Man Yun

New Power MOSFET Employing Segmented Trench Body Contact for Improving the Avalanche Energy

We have fabricated the 60 V power MOSFET employing the segmented trench body contact which results in low conduction loss and high avalanche energy (EAS) under undamped inductive switching (UIS) condition without sacrificing the device area. The proposed device employs the CMOS compatible deep Si trench process. The segmented trench body contact suppresses the hole current beneath the n+ source region under the avalanche breakdown mode because the impact ionization begins at the bottom of the trench contact, which suppresses the activation of parasitic NPN bipolar transistor and improves the EAS. We have investigated the avalanche characteristics by testing devices under UIS. The measured EAS of the proposed device is 4.5 mJ while that of the conventional one is 1.84 mJ. Although the breakdown voltage decreased from 69.8 V to 60.4 V by 13% due to the trench body contact, EAS improved by 144%. Trench segmentation increases the n+ source contact area which results in reducing the on- resistance and improving the uniformity of the trench body contact and active cells.

A simulation study on novel field stop IGBTs using superjunction

Performing device simulation, a novel insulated gate bipolar transistor (IGBT) that employs the superjunction as well as field stop (FS), has been investigated. For a planar 1200-V IGBT, the novel superjunction FS IGBT demonstrates the remarkable device performance such as the ON-state voltage drop of 1.6 V and switching-off energy of 20 /spl mu/J/A at the collector current density of 100 A/cm/sup 2/, which is considered as the best tradeoff performance in its class. In addition, the impact of various design parameters on device performance has been explored, and a comprehensive analysis for understanding of the operating mechanism is presented, which will be of help for realizing the SJFS IGBTs with optimum design.

Hot-Carrier-Stress-Induced Degradation of 1 kV AlGaN/GaN HEMTs by Employing SiO2 Passivation

High-voltage AlGaN/GaN HEMTs (high-electron-mobility transistors) are fabricated by employing SiO2 passivation and the degradation due to the hot carrier stress has been investigated. Our experimental result shows that the SiO2 passivation of AlGaN/GaN HEMT successfully achieves the breakdown voltage of 1 kV without any field plate design. The pulsed I-V measurement for AlGaN/GaN HEMT shows that the SiO2 passivation suppresses the frequency dispersion and decreases the on-resistance from 2.46 to 1.38 mOmega-cm2. The hot carrier stress degrades the electric characteristics of AlGaN/GaN HEMT because the high field increases the trapping at the surface and the interface. However, the SiO2 passivation of AlGaN/GaN HEMT decreases the surface trapping and 2DEG depletion during the hot carrier stress, so that a passivated device exhibits less degradation than an unpassivated one. After the hot carrier stress with VDS=30 V and VGS=10 V is applied to the device for 5times104 sec, the SiO2 passivation decreases the stress-induced degradation of forward drain current from 30.4 to 24.5 %.

A New Soft Self-Clamping Scheme for Improving the Self-Clamped Inductive Switching (SCIS) Capability of Automotive Ignition IGBT

The improvement of self-clamped inductive switching (SCIS) capability of ignition IGBT widely used in automotive coil driver ensures the protection of the ignition IGBT from a severe thermal stress under the abnormal switching condition such as the open secondary. We have proposed and verified a new self-clamping scheme for improving the self-clamped inductive switching (SCIS) capability of ignition IGBT by employing the collector coupled turn-on of IGBT. The proposed self-clamped IGBT has an additional power MOSFET connected between the gate and collector of main IGBT with a large gate resistance. The additional power MOSFET is turned-on temporarily at the beginning of the self-clamping mode, which increases the collector voltage of main IGBT gradually so that the proposed self-clamped IGBT reduces the hard switching energy loss, which results in improvement of the SCIS capability of main IGBT.

Investigation of Gate Oscillation of Power MOSFETs Induced by Avalanche Mode Operation

Serious gate oscillation of power MOSFETs under avalanche condition has been observed, degrading an avalanche withstanding capability. Using experiments as well as numerical simulation, it is shown that this gate oscillation in avalanche mode results from the impact ionized hole carrier accumulation on the surface under the gate oxide and the associated reciprocation between the gate of each unit cell with parasitic elements, which comes from a different phase of a gate capacitance according to a local avalanche breakdown. Experimental results also show that the devices with a poly-cut gate structure and a smaller chip size demonstrate strong immunity against the gate oscillation, which also verifies the new gate oscillation mechanism.

Degradation of Avalanche Ruggedness of Power Diodes by Thermally Induced Local Breakdown

The investigations into the failure mechanism of the power diode during the undamped inductive load switching (UIS) are presented using experiments and numerical simulations. During the avalanche event, the temperature rise due to the localized avalanche current increases breakdown voltage and as a result, the location of the peak impact ionization moves around in the device. This behavior alters the current distribution under the UIS condition, depending on the initial location of breakdown. When the avalanche event starts at the edge termination, the avalanche current redistribution into the active area is limited, resulting in weak avalanche capability. Therefore, for high avalanche ruggedness, the diode should have the uniformly distributed avalanche current, which can be observed when the breakdown starts at the bottom of anode junction. In this work, it is shown that the avalanche capability of the power diodes during the UIS conditions is strongly dependent on the location of the initial breakdown and the mismatch of the termination design and starting material can significantly degrade the avalanche capability. Therefore, the power diode with high avalanche capability should be designed by elaborately controlling the location of initial breakdown.

Investigation of 1500V Non-Punch Through IGBT Using Carrier Lifetime Control and Anode Engineering

For high power applications, non-punch through (NPT) IGBTs are increasingly employed with a lot of benefits over punch through (PT) IGBTs. However, during switching off transition the lasting tail current significantly contributes to turn-off energy loss, which deteriorates the advantages of the NPT IGBTs especially in soft switching applications. In general, in order to reduce the turn-off energy loss and optimize trade-off performance, injection efficiency is simply controlled, which will only adjust the trade-off performances within a limited range. To generate the trade-off performances in a wider range, the carrier lifetime control as well as the anode engineering is simultaneously applied. In this work, the resultant empirical data for a 1500V NPT IGBT will be investigated. The relevant device issues and their implications will also be discussed for further improvement of NPT IGBTs.

A new fault current-sensing scheme for fast fault protection of the insulated gate bipolar transistor

A new fault current-sensing scheme employing the floating p-well for fast protection of the insulated gate bipolar transistor (IGBT) from the short-circuit faults is proposed and verified by employing 2D mixed mode simulation, based on the previous experimental results. The proposed floating p-well current-sensing scheme detects not the normal operating current but the fault current of the main IGBT by using the diode connected MOSFET and a resistor, when the short-circuit fault occurs. The diode-connected MOSFET eliminates the degradation of the forward voltage drop, because the floating p-well current does not flow under the normal operating condition due to the threshold voltage of the diode connected MOSFET. The proposed current sensor increases the protection speed without any additional delay time by the external blanking filter.

A New 1200 V Punch Through-Insulated Gate Bipolar Transistor with Protection Circuit Employing Lateral Insulated Gate Bipolar Transistor and Floating p-Well Voltage Sensing Scheme

A new 1200 V punch through-insulated gate bipolar transistor (PT-IGBT) with a protection circuit employing a lateral IGBT (LIGBT) and a floating p-well voltage sensing scheme is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The detection of the fault and gate voltage pull-down operations is achieved using the floating p-well sensing scheme. The LIGBT used as a pull-down transistor reduces the area of the protection circuit due to the enhanced current handling capability. The voltage saturation effect of a floating p-well voltage under the high voltage condition provides the 1200 V PT-IGBT with a reliable and rapid protection by preventing the gate oxide failure of the pull-down LIGBT and eliminating the blanking filter.

Experimental Investigation of Pulsed-Laser-Annealed Ultralow-Conduction-Loss 600-V Nonpunchthrough Insulated-Gate Bipolar Transistors

Using a double-pulsed-laser-annealing process, an ultralow-conduction-loss 600-V nonpunchthrough (NPT) insulated-gate bipolar transistor (IGBT) is realized with a highly activated anode structure. This ultralow conduction loss has not been achievable prior to this due to the limited thermal budget in conventional annealing processes. The laser-annealed NPT IGBT demonstrates the ON-state voltage drop from 1.17 to 1.49 V at the collector current density of 165 A/cm2, which implies that a wide range of tradeoff performance between the conduction and switching losses can be generated according to various requirements of applications. This brief presents the characteristics of the laser-annealed NPT IGBT, depending on the splits of laser-irradiation conditions, and the implications of the low thermal-budget annealing process.