Chorng-Kuang Wang

A dual-loop automatic gain control for infrared communication system

This paper presents a dual-loop automatic gain control (AGC) employed in a 10 Mbps infrared communication system. The AGC is composed of an exponential-type variable-gain amplifier, a shaping filter, a gain/buffer stage, a noncoherent envelope detector, and a pair of integrators that provide dual loop bandwidths. The switch and two integrators are realized by a proposed switched integrator technique. The fast acquisition is accomplished by a 500 kHz loop bandwidth at the initial acquisition state and followed by a 50 kHz loop bandwidth at the steady state. The AGC is implemented in 0.6 /spl mu/m SPTM CMOS technology. According to the post-layout simulation, it achieves an acquisition time of 5 /spl mu/s and provides a constant output of 1V/sub pp/ at a 50 /spl Omega/ load for 20 dB input signal amplitude range. The dual-loop AGC consumes 88 mW power from a single 3.3 V supply and occupies 1.8/spl times/1.8 mm/sup 2/ area.

A VLSI design of dual-loop automatic gain control for dual-mode QAM/VSB CATV modem

A digitized automatic gain control (DAGC) whose loop bandwidth can be automatically regulated by a digital quantizer is presented in this paper. The designed quantizer that only costs tens of gates provides the DAGC both with wide loop bandwidth for fast acquisition and narrow loop bandwidth for low AGC gain jitter in stable steady-state. The receive bandpass filter, variable gain amplifier (VGA), and digital control circuits have been implemented in VLSI using 0.8 /spl mu/m CMOS technology. For both 64-QAM and 8-VSB signals, the closed-loop experimental results show that the designed DAGC has input dynamic range from 229 mV/sub pp/ to 456 mV/sub pp/, transient mode bandwidth 1 kHz, steady-state bandwidth 90 Hz, settling time of step response less than 2 ms using 10 MHz clock for digital control chip.

A new VSB modulation technique and shaping filter design

In this paper, we propose a new approach for VSB modulation. A pair of complex digital filters are used to accomplish waveform shaping and VSB modulation simultaneously. By the use of longer tap length, the high stop band attenuation eliminates the need for SAW filters at the output stage. To verify our approach, we use the Zenith VSB HDTV system as a test vehicle. A pair of 79-tap raised cosine digital filters are derived, implemented, and tested.

A hardware efficient 64-QAM low-IF transceiver baseband for broadband communications

This paper presents a hardware efficient VLSI design of digital baseband for 64-QAM communication systems over the last-mile cable network. This VLSI system design involves a cost-efficient architecture of the adaptive equalizer and a two-phase linear architecture of the pulse shaping filters, which reduce the hardware requirement by a factor of four comparing with traditional quadrature direct form FIR filters. In this design, the two-fold carrier recovery loop possesses a pull-in range of /spl plusmn/100kHz (i.e. /spl plusmn/18, 500ppm of the symbol rate) and -82dBc jitter suppression. Based on the proposed multi-staged LMS-based fractionally-spaced equalizer, the receiver realizes the symbol spaced timing recovery in a /spl plusmn/200ppm tolerance of the symbol rate. The acquisition time of the proposed 64-QAM blind adaptive system is 7ms, and the transceiver reaches the operation speed of the case for 32.28Mb/s 64-QAM low-IF digital CATV system over NTSC 6MHz bandwidth channels. Using 0.35 /spl mu/m CMOS technology, the transceiver design occupies a chip area 5.5mm /spl times/ 5.5mm and power consumption 1.35W (1.0W for RX) when the power supply is 3.3V.

A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop

This paper proposes a two-fold carrier recovery loop that possesses /spl plusmn/25000-ppm pull-in range and 7-ms acquisition time for 64-QAM blind adaptive system. The carrier recovery system contains a prior wide-band loop to acquire a coarse carrier frequency and a posterior narrow-band loop to achieve -82 dBc jitter suppression. It can be applied to a 4.035-MHz low-IF cable modem system with the /spl plusmn/100-kHz frequency offset tolerance requirement. The two-fold carrier recovery loop operates in consecutive three stages, which are Costas carrier phase estimation, DDML carrier phase estimation, and DD-MMSE carrier phase estimation. The proposed architecture is hardware efficient since the three-staged operation shares most of the circuit functions.

All digital CDMA upstream transmitter and baseband VLSI design of head-end receiver for upstream cable networks

This paper presents an all digital DS-CDMA upstream transmitter arid a head-end baseband receiver for upstream cable/HFC networks. The upstream transmitter supports frequency agility of the carrier, QPSK and QAM constellations up to 64QAM, variable symbol rates from 160kchip/s to 5.12Mchip/s increasing by power of two, and direct-digital up-conversion to achieve accurate amplitude and phase of modulation. The transmitter consists of pulse shaping filter, half-band filter, cascaded integrator-comb (CIC) filter, and inverse SINC filter. The all digital head-end baseband receiver supports programmable quadrature amplitude modulation up to 64QAM. Fast timing and carrier recovery algorithms are adopted for burst mode transmission. Code acquisition can be achieved within 2 symbols, and the carrier acquisition can be achieved within 31 symbols. All digital timing recovery is designed with /spl plusmn/200ppm symbol timing offset tolerance and the carrier recovery can compensate /spl plusmn/100ppm of carrier frequency offset.