Chorng-Sii Hwang

A precise cyclic CMOS time-to-digital converter with low thermal sensitivity

In this paper, a precise cyclic CMOS time-to-digital converters (TDC) with low thermal sensitivity is proposed. Through compensation, the thermal sensitivity of the new cyclic time-to-digital converter is reduced dramatically. The proposed TDC possesses not only less thermal-sensitive resolution but also low cost and small chip size. The circuit was fabricated with TSMC 0.35 mum CMOS technology. The size of the circuit is 0.40 mm times 0.30 mm only. The experimental results show that a plusmn6% resolution variation of the new TDC was achieved within 0~100degC temperature range which is much better than plusmn25% of the original uncompensated version. The effective resolution is as fine as 58 ps at room temperature. The measurement rate is 33 kHz, at least.

A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction

In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-μm technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption.

A high-resolution and fast-conversion time-to-digital converter

This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast conversion. With the aid of the gate delay difference technique, the TDC can achieve a sub-gate delay resolution. The flash-type operation enables the TDC to resolve the time difference for fine conversion in less than one reference clock cycle. The differential non-linearity (DNL) can be less than /spl plusmn/0.03 LSB and integral non-linearity (INL) less than /spl plusmn/0.04 LSB. We confirm the results based on 0.35 /spl mu/m CMOS process technology.

A wide-range and fast-locking clock synthesizer IP based on delay-locked loop

A wide-range and fast-locking clock synthesizer IP based on delay-locked loop is proposed. The ROSC-type cyclic delay line is employed for clock generation. A frequency detector is designed to provide fast-locking capability and the frequency switching behavior like the traditional PLL-based clock synthesizer. This design also includes initial start-up circuitry to activate the whole system from unlimited delay. The proposed clock synthesizer can solve the problem of changing frequency comparing to the conventional DLL-based clock synthesizers. Simulation results show that the output frequency range can operate from 10 to 500 MHz. the HSPICE simulation results are based upon TSMC 0.35/spl mu/m 2P4M CMOS process with a 3.3V power supply voltage. The power is less than 30mW at the highest output frequency. The core area for the design is 0.095mm/sup 2/.

Dual-band CDR using a half-rate linear phase detector

This paper describes a dual-band clock and data recovery circuit using a new half-rate linear phase detector. With the proposed sampling scheme, the phase detector produces UP/DN signals with equal pulsewidth and thus eliminates the demand of current scaling in the charge pump. The test chip fabricated by CMOS 0.18 μm 1P6M process can operate at 2.7 and 1.62 Gbps which satisfies the DisplayPort standard. It can recover the NRZ data of a (27-1) PRBS with a bit error rate less than 10−12. The chip core occupies an area of 0.36 mm2. The power consumption is 50 mW at 2.7 Gbps with a 1.8 V supply voltage.

DLL-based programmable clock multiplier using differential toggle-pulsed latch

In this paper, a programmable clock multiplier based on delay-locked loop is presented. It provides a flexible set of multiplying factors for differential clock generation. With the aid of the newly proposed gated short pulse generator and the differential toggle-pulsed latch, the measured output frequency of the clock multiplier implemented in CMOS 0.18-μm technology is within 0.15~1.8 GHz. The core circuit occupies an area of 0.076 mm2. The rms and peak-to-peak jitter of the multiplied output clocks at 1.6 GHz is 1.45 and 12.36 ps, respectively.

Timing generator using dual delay-locked loop

In this paper, the new architecture of a timing generator using dual delay-locked loop (DLL) is proposed. With the aid of coarse and fine tuning mechanisms, the timing generator can provide sub-gate resolution with precise close-loop control and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.35 μm 2P4M technology. The chip area occupies 1.36 mm2. It can interpolate the reference clock cycle with 80 divisions to obtain 45 ps resolution when running at 280 MHz. The DNL and INL are within -0.3~+0.6 and -0.8~+0.4 LSB, respectively.

A spread spectrum clock generator using digital modulation scheme

This paper describes a new architecture of the spread-spectrum clock generator (SSCG) using direct digital modulation scheme on VCO. Differing from the conventional technique by altering the control voltage of VCO, the modulating operation is performed by the selection of multi-band VCO. The proposed SSCG test chip has been fabricated by CMOS 0.18mum 1P6M process. The operating frequency range is within 680~1,080MHz with the center-spread setting of 0.5% and 1%. The chip area is 0.68mm2. The peak reduction at 800MHz output clock can achieve 10.61dB and 12.52dB for ratios of 0.5% and 1%, respectively. The power consumption is 12mW at 800MHz.

High-Speed Continuous Time Digitizer Using a Two-Level Multiphase Sampling Technique

In this paper, the new architecture of a high-speed continuous time digitizer has been proposed. With the aid of a two-level multiphase sampling technique, the time digitizer can use only 16 delay cells and DFFs to perform the flash-type conversion of 64-stage interpolation. The time digitizer can obtain 78 ps resolution with a reference frequency running at 200 MHz. The continuous input clock frequency can be up to 250 MHz. The layout area occupies 1.08 mm2. A novel clock multiplier is also introduced to provide multiphase generation with frequency output range within 640 MHz ~1.8 GHz.

Continuous time digitizer utilizing multiphase sampling technique

In this paper, the new architecture of a high-speed continuous time digitizer is proposed. With the aid of a two-level multiphase sampling technique, the time digitizer can use only 16 delay cells and DFFs to perform the flash-type conversion of 64-stage interpolation. The time digitizer can obtain 78 ps resolution with a reference frequency running at 200 MHz. The continuous input clock frequency can be up to 250 MHz. The test chip is fabricated in TSMC 0.18 mum 1P6M mixed mode process. The layout area occupies 1.08 mm2. The DNL is within -0.62 ~ +0.51 and INL within -0.99 ~ +0.98. A novel clock multiplier is also introduced to provide multiphase generation with the frequency output range within 0.64 ~ 1.8 GHz.