Poki Chen

A time-to-digital-converter-based CMOS smart temperature sensor

A time-to-digital-converter-based CMOS smart temperature sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on voltage/current ADCs for digital output code conversion. For the purpose of cost reduction and power savings, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter is utilized to convert the pulse into a corresponding digital code. The test chips have an extremely small area of 0.175 mm/sup 2/ and were fabricated in the TSMC CMOS 0.35-/spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.7/spl sim/+0.9/spl deg/C after two point calibration, but without any curvature correction or dynamic offset cancellation. The effective resolution is better than 0.16/spl deg/C, and the power consumption is under 10 /spl mu/W at a sample rate of 2 samples/s.

A CMOS pulse-shrinking delay element for time interval measurement

A deep sub-nanosecond resolved CMOS pulse-shrinking delay element used in the time-to-digital converter (TDC) is proposed. The pulse shrinking capability of the element is controlled by the dimension ratio of the adjacent gates. This control mechanism is completely different from the bias adjustment adopted in the conventional pulse-shrinking element. Without the need of continuous calibration, the presented element possesses not only extremely fine resolution, small single-shot errors, low power consumption, but also good insensitivity to the supply voltage variation. Being fabricated with 0.35 /spl mu/m CMOS technologies, the TDC made of the new elements has been measured to have a resolution of 68 ps. The effective resolution only varies 1.5 ps for a rather large supply voltage range from 3.5 to 4.5 V. The size of the circuit is 0.35 mm/spl times/0.09 mm only, excluding the I/O pads. Under a single 3.3-V power supply, the static power dissipation, including the I/O pads, is 1 /spl mu/W. The average power consumption is measured to be merely 1.2 mW under a measurement rate of 100 ksps.

A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of −0.4°C ∼ +0.6°C Over a 0°C to 90°C Range

This paper describes a time-domain temperature sensor based on a successive approximation algorithm. Without using any bipolar transistor, a temperature sensor composed of a temperature-dependent delay line (TDDL) is utilized to generate a delay proportional to the measured temperature. A binary-weighted adjustable reference delay line (ARDL) is adopted with an effective delay varied by a SAR control logic to approximate the TDDL delay for output coding. For linearity enhancement, a curvature compensation between both delay lines is invented to achieve the best ever accuracy among inverter-delay-based smart temperature sensors. With two-point calibration, a -0.4°C ˜ +0.6°C inaccuracy (3σ) over a 0°C ˜ 90°C temperature operation range has been measured for 23 test chips. With 10 output bits, the proposed sensor achieves a resolution better than 0.1°C and a chip area of 0.6 mm2 in a TSMC 0.35-μm standard digital CMOS process. The sensors average current consumption is 11.1 μA at a conversion rate of 2 samples/s.

A Fully Digital Time-Domain Smart Temperature Sensor Realized With 140 FPGA Logic Elements

To explore the possibility of soft intellectual property implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or system-on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the pulse with a temperature-proportional width. The timing reference is just the input clock and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit was implemented by field-programmable gate array chips for functionality verification and performance evaluation. Realized with as few as 140 logic elements, the proposed smart sensor was measured to have an error of -1.5 ~ 0.8 degC over the full commercial IC temperature operation range of 0 degC-75 degC for thermal self-sensing or monitoring. The effective resolution can be made better than 0.1 degC easily, and the power consumption is 8.42 muW at a sampling rate of 2 samples/s. The longest conversion time is around 260 s, and a conversion rate of 3 kHz at least is promised.

All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of

To get rid of the heavy burden of aspect ratio tuning, bias adjustment and porting problem among processes in full-custom or mixed-mode design, a fully digital smart temperature sensor realizable with 140 field programmable gate array (FPGA) logic elements was proposed for painless VLSI on-chip integrations. By simply replacing the cyclic delay line with a retriggerable ring oscillator for accuracy enhancement, modifying the gain of time amplifier from fixed to variable for one-point calibration support and adopting a second-order master curve for curvature correction in this paper, the proposed smart temperature sensor can achieve two thirds reduction in circuit size, at least four-fold improvement in power consumption and more than two-fold enhancement in accuracy. To demonstrate the performance under practical process variation, the sensor realized with as few as 48 FPGA logic elements for rapid prototyping was measured over 0°C to 100°C range for 20 test chips from batches spreading over 4 years. The measured inaccuracy is -0.7°C-+0.6°C which is superior to -1.8°C-+2.3°C of its full-custom predecessor with a third-order master curve and five test samples from one single batch. The accuracy is even better than those of full-custom sensors with two-point calibration. The conversion rate is around 4.4 kHz and the power consumption can be reduced to 175 nJ per conversion by increasing the number of delay stages in ring oscillator to 4608.

-{\hbox {0.7}} ~^{\circ}{\hbox {C}}-+{\hbox {0.6}}~^{\circ}{\hbox {C}}

A low-cost and low-power CMOS time-to-digital converter (TDC) with 50-ps time resolution is proposed in this paper. The reference clock frequency of the TDC is 80 MHz and the input range is theoretically unlimited. Two parallel time interpolators are used to improve the resolution by pulse stretching. In addition to conventional current ratio and capacitor ratio, the duty cycle of the discharging clock is also incorporated to adjust the stretch factor to reduce the power consumption and chip area dramatically. The interpolators are based on analog dual-slope conversion. The time resolution is measured as 50 ps and the integral nonlinearity (INL) error is within plusmn1.1 LSB for input range up to 250ns. The temperature drift of the measured resolution is -15.2% to +13% over a temperature range of -40degC to 80degC, which is significantly smaller than plusmn125% drift over 100degC temperature range in previous work. The voltage drift is 3.8 ps/V or equivalently plusmn3.5% over 3.0-4.0 V supply voltage range. The measured resolution is within 49.8 ps to 52.7 ps for six packaged chips and the chip size is merely 0.5 mmtimes0.45mm as fabricated in the TSMC 0.35-mum CMOS digital process. The power consumption is 0.75mW, enormously reduced from hundreds of milliwatts of the predecessors, at 100 k samples/s and the measurement rate can achieve as high as 150 k samples/s

After One-Point Calibration

A monolithic Vernier-based time-to-digital converter (TDC) with 37.5 ps time resolution and theoretically unlimited input range has been integrated in TSMC 0.35-mum standard 2P4M CMOS technology. Since the proposed circuit utilizes a single-stage Vernier delay line (VDL) for both coarse and fine measurements, no other interpolation circuit is required. The operation frequencies of the single-stage Vernier delay line are stabilized against process, voltage and temperature (PVT) variations by dual phase-locked loops. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured differential nonlinearity is plusmn0.2 LSB, and the measured integral nonlinearity is plusmn0.35 LSB. The power consumption is 150 mW at 100 k samples/s full conversion speed, and the chip size is as small as 0.222 mm2. All the packaged chips were tested to be fully functional over -40degC to 100degC ambient temperature range and 3.0 V to 3.9 V supply voltage range with extremely low resolution variations

A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching

In this paper, a precise cyclic CMOS time-to-digital converters (TDC) with low thermal sensitivity is proposed. Through compensation, the thermal sensitivity of the new cyclic time-to-digital converter is reduced dramatically. The proposed TDC possesses not only less thermal-sensitive resolution but also low cost and small chip size. The circuit was fabricated with TSMC 0.35 mum CMOS technology. The size of the circuit is 0.40 mm times 0.30 mm only. The experimental results show that a plusmn6% resolution variation of the new TDC was achieved within 0~100degC temperature range which is much better than plusmn25% of the original uncompensated version. The effective resolution is as fine as 58 ps at room temperature. The measurement rate is 33 kHz, at least.

A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy

A novel cyclic time-to-digital converter (TDC) is proposed in this paper. The measured resolution (or LSB width equivalent) can reach 68 picoseconds, and the corresponding single-shot errors are around 1/2 LSB width. Under a single 3.3 V power supply, the stand-by current consumption is measured to be 0.3 mA only, including the I/O pads. The operation current consumption is measured to be 370 uA under 100 k/sec measurement rate.

A precise cyclic CMOS time-to-digital converter with low thermal sensitivity

The first FPGA multiple channel digital-to-time converter, or digital pulse generator, is proposed to further extend FPGA applications into analog domain. Based on vernier principle, the effective resolution is made equivalent to the period difference of two phase-locked loop (PLL) outputs. The finer than ever DTC resolution of 1.58 ps is achieved with an Altera Stratix III FPGA chip. The DNL and INL are verified to be -0.086 ~ +0.12 LSB and -0.93 ~ +0.75 LSB respectively for input value varied from 1 to 1026. The widest operation range of 59.3 minutes is accomplished with 51 functioning input bits. Except for 2 shared PLLs, there are only 422 combinational ALUTs and 84 dedicated logic registers utilized per channel for 224-channel circuit implementation. The power consumption per channel is simulated to be 3.04 mW only. With a simple but powerful structure, the design cost is substantially reduced from those of its predecessors.