Chris Cork

Implications of triple patterning for 14nm node design and patterning

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

Interactions of double patterning technology with wafer processing, OPC and design flows

Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability

Double patterning technology (DPT) is one of the most practical candidate technologies for 45nm half-pitch or beyond while conventional single exposure (SE) is still dominant with hyper NA avoiding DPT difficulties such as split-conflict or overlay issue. However small target dimension with hyper NA and strong illumination causes OPC difficulty and small latitude of lithography and photomask fabricated with much tight specification are required for SE. Then there must be double patterning (DP) approach even for SE available resolution. In this paper DP for SE available resolution is evaluated on lithography performance, pattern decomposition, photomask fabrication and inspection load. DP includes pattern pitch doubled of SE, then lithography condition such as mask error enhancement factor (MEEF) is less impacted and the lower MEEF means less tight specification for photomask fabrication. By using Synopsys DPT software, there are no software-induced conflicts and stitching is treated to be less impact. And also this software detects split-conflicts such as triangle or square placement from contact spacing. For estimating photomask inspection load, programmed defect pattern and circuit pattern on binary mask are prepared. Smaller MEEF leads less impact to defect printing which is confirmed with AIMS evaluation. As an inspection result, there are few differences of defect sensitivity for only dense features and also few differences of false defect counts between SE and DP with less NA. But if higher NA used, DPs inspection sensitivity is able to be lowered Then inspection load for DP would be lighter than SE.

Double-Patterning-Friendly OPC

Double patterning technology (DPT) is one of the main options for printing critical layers at 32nm half-pitch and beyond. To enable DPT, a layout decomposition tool is first used to split the original design into two separate decomposed-design layouts. Each decomposed-design layout may then receive optical proximity correction (OPC) and RETs to produce a mask layout. The requirements for OPC to enable individual layer DPT patterning are generally the same as current single exposure OPC requirements, meaning that the success criteria will be similar to previous node specifications. However, there are several new challenges for OPC with DPT. These include large litho-etch biases, two sets of process variables associated with each patterning layer and the relative pattern placement between them. The order of patterning may be important as there may be process interactions between the two patterns especially at overlap regions. Corners which were rounded in single patterning layers may now become sharp, potentially increasing reliability concerns due to electromigration. In this study, we address many of these issues by proposing several new techniques that can be used in OPC with DPT. They are specifically designed for the Litho-Etch-Litho-Etch process, but some of the ideas may be extended to develop OPC methods for other DPT processes. We applied the new OPC method to several circuit and test patterns and demonstrated how OPC results were improved compared to regular OPC methods.

Optical proximity correction challenges with highly elliptical contacts

The steady march of Moores law demands ever smaller feature sizes to be printed and Optical Proximity Correction to correct to ever tighter dimensional tolerances. Recently pitch doubling techniques has relieved the pressure on CD reduction, which instead of being achieved lithographically are reduced by subsequent etching or chemical interaction with spin-on layers. CD tolerance reductions, however, still need to match the overall design rule shrinkage. The move to immersion lithography, where effective Numerical Apertures now reach 1.35, has been accompanied by a significantly reduction in depth of focus, especially on isolated contacts. To remedy this, RET techniques such as assist feature placement, have been implemented. Certain local placements of assist features and neighboring contacts are observed to result in highly elliptical contacts being printed. In some layouts small changes in the aspect ratio of the contact on the mask leads to strong changes in the aspect ratio of the printed contact, whereas in other layouts the response is very weak. This effect can be described as an aspect ratio MEEF. The latter type of contact can pose a significant challenge to the OPC recipe which is driven by the need to place the printed contour within a small range of distance from target points placed on the midpoint of edges of a nominally square contact. The OPC challenge naturally will be compounded when the target layout is rectangular in the opposite sense to the natural elliptical shape of the printed contact. Approaches to solving this can vary from intervening at the assist feature placement stage, at the possible loss of depth of focus, to accepting a certain degree of ellipticity in the final contour and making the OPC recipe concentrate on minimizing any residual errors. This paper investigates which contact layouts are most challenging, discusses the compromises associated with achieving the correction target and results are shown from a few different approaches to resolving these issues.

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Delays in equipment availability for both Extreme UV and High index immersion have led to a growing interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves decomposing a layout into two masking layers that are printed and etched separately so as to provide the intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of layout can be clearly identified and avoided based on short range interactions, compliance issues can also extend over large areas of the design and are hard to recognize. This means certain design practices should be implemented to provide suitable breaks or performed with layout tools that are double patterning compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at the minimum design space rather than the relaxed space intended. Another equally important class of compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often presented with multiple options for where to cut the design thereby defining an area of overlap between the different printed layers. While these overlap areas can have markedly different topologies (for instance the overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which cannot be decomposed or which can only be decomposed with poor manufacturability need to be highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an internally developed automated double pattern decomposition tool to investigate design compliance and describes a number of classes of non-conforming layout. Tool results then provide help to the designer to achieve robust design compliant layout.

Patterning control budgets for the 32-nm generation incorporating lithography, design, and RET variations

An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed. In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.

An economic analysis for optimal distributed computing resources for mask synthesis and tape-out in production environment

With the exponential increase in output database size due to the aggressive optical proximity correction (OPC) and resolution enhancement technique (RET) required for deep sub-wavelength process nodes, the CPU time required for mask tape-out continues to increase significantly. For integrated device manufacturers (IDMs), this can impact the time-to-market for their products where even a few days delay could have a huge commercial impact and loss of market window opportunity. For foundries, a shorter turnaround time provides a competitive advantage in their demanding market, too slow could mean customers looking elsewhere for these services; while a fast turnaround may even command a higher price. With FAB turnaround of a mature, plain-vanilla CMOS process of around 20-30 days, a delay of several days in mask tapeout would contribute a significant fraction to the total time to deliver prototypes. Unlike silicon processing, masks tape-out time can be decreased by simply purchasing extra computing resources and software licenses. Mask tape-out groups are taking advantage of the ever-decreasing hardware cost and increasing power of commodity processors. The significant distributability inherent in some commercial Mask Synthesis software can be leveraged to address this critical business issue. Different implementations have different fractions of the code that cannot be parallelized and this affects the efficiency with which it scales, as is described by Amdahl’s law. Very few are efficient enough to allow the effective use of 1000’s of processors, enabling run times to drop from days to only minutes. What follows is a cost aware methodology to quantify the scalability of this class of software, and thus act as a guide to estimating the optimal investment in terms of hardware and software licenses.

Suppressing ringing effects from very strong off-axis illumination with novel OPC approaches for low k1 lithography

With the delay in commercialization of EUV and the abandonment of high index immersion, Fabs are trying to put half nodes into production by pushing the k1 factor of the existing scanner tool base as low as possible. A main technique for lowering lithographic k1 factor is by moving to very strong offaxis illumination (i.e., illumination with high outer sigma and a narrow range of illumination angles), such as Quadrapole (e.g., C-Quad), custom or even dipole illumination schemes. OPC has generally succeeded to date with either rules-based or simple model-based dissection together with target point placement schemes. Very strong off-axis illumination, however, creates pronounced ringing effects on 2D layout and this makes these simpler dissection techniques problematic. In particular, it is hard to prevent overshoot of the contour around corners while simultaneously dampening out the ringing further down the feature length. In principle, a sufficiently complex set of rules could be defined to solve this issue, but in practice this starts to become un-manageable as the time needed to generate a usable recipe becomes too long. Previous implementations of inverse lithography demonstrated that good CD control is possible, but at the expense of the mask costs and other mask synthesis complications/limitations. This paper first analyzes the phenomenon of ringing and the limitations seen with existing simpler target placement techniques. Then, different methods of compensation are discussed. Finally, some encouraging results are shown with new traditional and inverse experimental techniques that the authors have investigated, some of which only demand incremental changes to the existing OPC framework. The results show that new OPC techniques can be used to enable successful use of very strong off-axis illumination conditions in many cases, to further reduce lithographic k1 limits.

Parallel Processing for Pitch Splitting Decomposition

Decomposition of an input pattern in preparation for a double patterning process is an inherently global problem in which the influence of a local decomposition decision can be felt across an entire pattern. In spite of this, a large portion of the work can be massively distributed. Here, we discuss the advantages of geometric distribution for polygon operations with limited range of influence. Further, we have found that even the naturally global coloring step can, in large part, be handled in a geometrically local manner. In some practical cases, up to 70% of the work can be distributed geometrically. We also describe the methods for partitioning the problem into local pieces and present scaling data up to 100 CPUs. These techniques reduce DPT decomposition runtime by orders of magnitude.