Levi D. Barnes

Interactions of double patterning technology with wafer processing, OPC and design flows

Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

In this paper we study interactions of double patterning technology (DPT) with lithography, optical proximity correction (OPC) and physical design flows for the 22-nm device node. DPT methods decompose the original design intent into two individual masking layers, which are each patterned using single exposures and existing 193-nm lithography tools. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step that will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons, where required, and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals, such as reduce circuit area, minimize relayout effort, ensure DPT compliance, guarantee patterning robustness on individual layer targets, ensure symmetric wafer results, and create uniform wafer density for the individual patterning layers.

Model-based assist feature placement using inverse imaging approach

The continuing reduction in feature dimensions and tightening of process constraints have led to an increasing demand for model-based approaches, which can efficiently explore the AF solution space, and achieve AF configurations not easily accessible via rules. In this work, we approach the AF placement problem as an inverse imaging problem. We discuss the generation of an inverse mask field and its use in determining the assist feature location. The results are compared with the single iteration intensity-field based AF placement with regard to symmetry, speed, memory, convergence, and accuracy. Several results with different pitches and illumination conditions are presented to demonstrate the robustness and adaptability of the inverse mask AF placement.

Model-based placement and optimization of subresolution assist features

Sub-resolution assist features (SRAFs) are an important tool for improving through-process robustness of advanced lithographic processes. Assist features have generally been placed and adjusted according to heuristic rules. The complexity of these rules increases rapidly with shrinking features size requiring more wafer data for calibration and more effort on the part of engineers. For advanced nodes, a model-based approach may better account for the variety of two-dimensional geometries and reduce substantially the amount of user effort required for effective SRAF placement. There are many ways in which model-based methods can be used to improve the effectiveness of assist features; we investigate several here. In the investigations described here, process window models may be employed to: 1) derive optimal rules for initial AF placement in a rule-based process, 2) resolve mask rule violations in optimal ways, and 3) make post-placement corrections of mask sites with poor behavior. In addition, we discuss a method for replacing an initial rule-based assist feature placement with a model-based placement which can consider the local two-dimensional geometry.

Double-Patterning-Friendly OPC

Double patterning technology (DPT) is one of the main options for printing critical layers at 32nm half-pitch and beyond. To enable DPT, a layout decomposition tool is first used to split the original design into two separate decomposed-design layouts. Each decomposed-design layout may then receive optical proximity correction (OPC) and RETs to produce a mask layout. The requirements for OPC to enable individual layer DPT patterning are generally the same as current single exposure OPC requirements, meaning that the success criteria will be similar to previous node specifications. However, there are several new challenges for OPC with DPT. These include large litho-etch biases, two sets of process variables associated with each patterning layer and the relative pattern placement between them. The order of patterning may be important as there may be process interactions between the two patterns especially at overlap regions. Corners which were rounded in single patterning layers may now become sharp, potentially increasing reliability concerns due to electromigration. In this study, we address many of these issues by proposing several new techniques that can be used in OPC with DPT. They are specifically designed for the Litho-Etch-Litho-Etch process, but some of the ideas may be extended to develop OPC methods for other DPT processes. We applied the new OPC method to several circuit and test patterns and demonstrated how OPC results were improved compared to regular OPC methods.

Improvements in model-based assist feature placement algorithms

Demanding process window constraints have increased the need for effective assist feature placement algorithms that are robust and flexible. These algorithms must also allow for quick ramp up when changing nodes or illumination conditions. Placement based on the optical components of real process models has the potential to satisfy all of these requirements. We present enhancements to model-based assist feature algorithms. These enhancements include exploration of image-processing techniques that can be exploited for contact-via AF placement, model-based mask rule check (MRC) conflict resolution, the application of models to line-space patterns, and a novel placement technique for contact-via layers using a specially-built single modeling kernel.

Optical proximity correction challenges with highly elliptical contacts

The steady march of Moores law demands ever smaller feature sizes to be printed and Optical Proximity Correction to correct to ever tighter dimensional tolerances. Recently pitch doubling techniques has relieved the pressure on CD reduction, which instead of being achieved lithographically are reduced by subsequent etching or chemical interaction with spin-on layers. CD tolerance reductions, however, still need to match the overall design rule shrinkage. The move to immersion lithography, where effective Numerical Apertures now reach 1.35, has been accompanied by a significantly reduction in depth of focus, especially on isolated contacts. To remedy this, RET techniques such as assist feature placement, have been implemented. Certain local placements of assist features and neighboring contacts are observed to result in highly elliptical contacts being printed. In some layouts small changes in the aspect ratio of the contact on the mask leads to strong changes in the aspect ratio of the printed contact, whereas in other layouts the response is very weak. This effect can be described as an aspect ratio MEEF. The latter type of contact can pose a significant challenge to the OPC recipe which is driven by the need to place the printed contour within a small range of distance from target points placed on the midpoint of edges of a nominally square contact. The OPC challenge naturally will be compounded when the target layout is rectangular in the opposite sense to the natural elliptical shape of the printed contact. Approaches to solving this can vary from intervening at the assist feature placement stage, at the possible loss of depth of focus, to accepting a certain degree of ellipticity in the final contour and making the OPC recipe concentrate on minimizing any residual errors. This paper investigates which contact layouts are most challenging, discusses the compromises associated with achieving the correction target and results are shown from a few different approaches to resolving these issues.

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Delays in equipment availability for both Extreme UV and High index immersion have led to a growing interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves decomposing a layout into two masking layers that are printed and etched separately so as to provide the intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of layout can be clearly identified and avoided based on short range interactions, compliance issues can also extend over large areas of the design and are hard to recognize. This means certain design practices should be implemented to provide suitable breaks or performed with layout tools that are double patterning compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at the minimum design space rather than the relaxed space intended. Another equally important class of compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often presented with multiple options for where to cut the design thereby defining an area of overlap between the different printed layers. While these overlap areas can have markedly different topologies (for instance the overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which cannot be decomposed or which can only be decomposed with poor manufacturability need to be highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an internally developed automated double pattern decomposition tool to investigate design compliance and describes a number of classes of non-conforming layout. Tool results then provide help to the designer to achieve robust design compliant layout.

Assist feature placement analysis using focus sensitivity models

Sub-Resolution Assist Features (SRAFs) are placed into patterns to enhance the through process imaging performance of critical features. SRAFs are typically placed using complex rules to achieve optimal configurations for a pattern. However, as manufacturing process nodes are growing increasingly complex, the SRAF placement rules will most likely be unable to produce optimal performance on some critical features. A primary impediment to resolving these problems is identifying poorly performing features in an efficient manner. A new process model form referred to as a Focus Sensitivity Model (FSM) is capable of rapidly analyzing SRAF placement for through process pattern performance. This study will demonstrate that an FSM is capable of finding suboptimal SRAF placements as well as missing SRAFs. In addition, the study suggests that the FSM does not need to comprehend the entire photolithography process to analyze SRAF placement. This results in simpler models that can be generated before a manufacturing process enters its development phase.

Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows

In double-patterning technology (DPT), we study the complex interactions of layout creation, physical design and design rule checking flows for the 22nm and 16nm device nodes. Decomposition includes the cutting (splitting) of original design-intent features into new overlapping polygons where required; and the coloring of all the resulting polygons into two mask layouts. We discuss the advantages of geometric distribution for polygon operations with the limited range of influence. Further, we find that even the naturally global coloring step can be handled in a geometrically local manner. We analyze and compare the latest methods for designing, processing and verifying DPT methods including the 22nm and 16nm nodes.