Kevin Lucas

Improving model-based OPC performance for the 65-nm node through calibration set optimization

As lithography continues to increase in difficulty with low k1 factors, and ever-tighter process margins, model-based optical proximity correction (OPC) is being used for the majority of patterning layers. As a result, the engineering effort consumed by the development and calibration of OPC models is continuing to increase at an alarming rate. One of the major focal points of this effort is the increasing emphasis on improving the accuracy of the model-based OPC corrections. One of the major contributors to final OPC accuracy is the quality of the resist model. As a result of these trends, the number of sample points used to calibrate OPC models is increasing rapidly from generation to generation. However, this increase is largely due to an antiquated approach to the construction of these calibration sets, focusing on structure variations. In this study, a new approach to the calibration of a resist model will be proposed based upon the location of calibration structures within the actual resist space over which the resist model is expected to be predictive.

High accuracy 65nm OPC verification: full process window model vs. critical failure ORC

It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.

Logic design for printability using OPC methods

The steps that create physical shape data in a typical logic device design-to-reticle flow are cell layout, place and route, tapeout, OPC or RET, data fracture, and reticle build. Here, we define OPC as the transformation of reticle data to compensate for lithographic and process distortions so that the final wafer pattern is as close to the target pattern-the designed layout-as possible. We define RETs as the general class of transformations for reticle data that aim to improve the patterning process window; therefore, OPC is a subset of RET. DFM is traditionally considered to be implemented at the cell layout or routing stages of this flow. Examples include the optimization of a layout based on critical-defect area, the addition of redundant contacts and vias, wire spreading, upsizing of metal landing pads, and the addition of dummy metal tiles to improve the planarity after chemical-mechanical planarization (CMP). We presented a detailed analysis of these techniques in an earlier work. In contrast, this article analyzes the possibility of extending these traditional methods into the OPC stage and introduces new post-tapeout RET methods for improving printability.

Investigation of model-based physical design restrictions (Invited Paper)

As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industrys transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.

Optical issues of thin organic pellicles in 45-nm and 32-nm immersion lithography

The semiconductor industry will soon be putting >=1.07NA 193nm immersion lithography systems into production for the 45nm device node and in about three years will be putting >=1.30NA systems into production for the 32nm device node. For these very high NA systems, the maximum angle of light incident on a 4X reticle will reach ~16 degrees and ~20 degrees for the 45nm and 32nm nodes respectively. These angles can no longer be accurately approximated by an assumption of normal incidence. The optical diffraction and thin film effects of high incident angles on the wafer and on the photomask have been studied by many different authors. Extensive previous work has also investigated the impact of high angles upon hard (e.g., F-doped silica) thick (>700μm) pellicles for 157nm lithography, e.g.,. However, the interaction of these high incident angles with traditional thin (< 1μm) organic pellicles has not been widely discussed in the literature. In this paper we analyze the impact of traditional thin organic pellicles in the imaging plane for hyper-NA immersion lithography at the 45nm and 32nm nodes. The use of existing pellicles with hyper-NA imaging is shown to have a definite negative impact upon lithographic CD control and optical proximity correction (OPC) model accuracy. This is due to the traditional method of setting organic pellicle thickness to optimize normally incident light transmission intensity. Due to thin film interference effects with hyper-NA angles, this traditional pellicle optimization method will induce a loss of high spatial frequency (i.e., high transmitted angle) intensity which is similar in negative impact to a strong lens apodization effect. Therefore, using simulation we investigate different pellicle manufacturing options (e.g., multi-layer pellicle films) and OPC modeling options to reduce the high spatial frequency loss and its impact.

Correction of long-range effects applied to the 65-nm node

Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows. For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.

65nm OPC and design optimization by using simple electrical transistor simulation

In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance: 1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects. 2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples: -design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor. -Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.

High transmission mask technology for 45nm node imaging

The lithography prognosticator of the early 1980’s declared the end of optics for sub-0.5μm imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several authors have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges. The requirements stated in the ITRS roadmap for current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will continue further for aggressive imaging solutions. Lithography and more importantly “imaging solutions” are driven by economics. The technology might be extremely innovative and “fun”, however, if its too expensive it may never see the light of scanner. The authors have investigated and compared the capability of high transmission mask technology and image process integration for the 45nm node. However, the results will be graded in terms of design, mask manufacturability, imaging performance and overall integration within a given process flow.

Sensitivity of a variable threshold model toward process and modeling parameters

The quality of model-based OPC correction depends strongly on how the model is calibrated in order to generate a resist image as close to the desired shapes as possible. As the k1 process factor decreases and design complexity increases, the correction accuracy and the model stability become more important. It is also assumed that the stability of one model can be tested when its response to a small variation in one or several parameters is small. In order to quantify this, the small-variation method has been tested on a variable threshold based model initially optimized for the 65nm node using measurements done with a test pattern mask. This method consists of introducing small variations to one input model parameter and analyzing the induced effects on the simulated edge placement error (EPE). In this paper, we study the impact of small changes in the optical and resist parameters (focus settings, inner and outer partial coherent factors, NA, resist thickness) on the model stability. And then, we quantify the sensitivity of the model towards each parameter shift. We also study the effects of modeling parameters (kernel count, model fitness, optical diameter) on the resulting simulated EPE. This kind of study allows us to detect coverage or process window problems. The process and modeling parameters have been modified one by one. The ranges of variations correspond to those observed during a typical experiment. Then the difference in simulated EPE between the reference model and the modified one has been calculated. Simulations show that the loss in model accuracy is essentially caused by changes in focus, outer sigma and NA and lower values of optical diameter and kernel count. Model results agree well with a production layout.

Reticle enhancement verification for the 65nm and 45nm nodes

In the last 2 years, the semiconductor industry has recognized the critical importance of verification for optical proximity correction (OPC) and reticle/resolution enhancement technology (RET). Consequently, RET verification usage has increased and improved dramatically. These changes are due to the arrival of new verification tools, new companies, new requirements and new awareness by product groups about the necessity of RET verification. Currently, as the 65nm device generation comes into full production and the 45nm generation starts full development, companies now have the tools and experience (i.e., long lists of previous errors to avoid) needed to perform a detailed analysis of what is required for 45nm and 65nm RET verification. In previous work [1] we performed a theoretical analysis of OPC & RET verification requirements for the 65nm and 45nm device generations and drew conclusions for the ideal verification strategy. In this paper, we extend the previous work to include actual observed verification issues and experimental results. We analyze the historical experimental issues with regard to cause, impact and optimum verification detection strategy. The results of this experimental analysis are compared to the theoretical results, with differences and agreement noted. Finally, we use theoretical and experimental results to propose an optimized RET verification strategy to meet the user requirements of 45nm development and the differing requirements of 65nm volume production.