Chris Rowen

Energy-Efficient Computing for Extreme-Scale Science

A many-core processor design for high-performance systems draws from embedded computings low-power architectures and design processes, providing a radical alternative to cluster solutions.

Reducing SoC simulation and development time

Looks at how, by using extensible processors, designers can develop and verify task engines for many embedded system-on-chip tasks more quickly than by using the traditional RTL-defined hardware design approach.

Flexible architectures for engineering successful SOCs

This paper focuses on a particular SOC design technology and methodology, here called the advanced or processor-centric SOC design method, which reduces the risk of SOC design and increases ROI hy using configurahle processors to implement onchip functions while increasing the SOCs flexibility through software programmability. The essential enabler for this design methodology is automatic processor generation-the rapid and easy creation of new microprocessor architectures, complete with efficient hardware designs and comprehensive software tools. The high speed of the generation process and the great flexibility of the generated architectures underpin a fundamental shift of the role of processors in system architecture.

A DSP architecture optimized for wireless baseband

The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations such as LTE. The Tensilica ConnX Baseband Engine processor core implements a 3-issue VLIW, 8-way SIMD architecture. It can perform 16 multiply-add operations per cycle, and executes a full radix-4 FFT butterfly or 4 complex FIR filter taps per cycle. It directly implements vector division and reciprocal square root operations. At 400MHz, it provides almost 13GB per second of memory bandwidth. The rich programming environment, including vectorization of scalar C applications, allows easy deployment into cellular base-station, femto-cell and other software-agile radio applications, and into multi-standard broadcast receivers.

Configurable Multi-Processor Platforms for Next Generation Embedded Systems

Next-generation embedded systems in application domains such as multimedia, wired and wireless communications, and multipurpose portable devices, are increasingly turning to multiprocessor platforms as a vehicle for their realization. But entirely fixed platforms composed of entirely fixed components lack the flexibility and ability to be optimized to the application to offer the best solution in any of these areas. Configurability at multiple levels offers a much better chance to optimize the resulting multiprocessor platform. Existing and emerging technologies for configurable and extensible processors and the creation of configurable multiprocessor subsystem platforms offer significant capability to design teams to both differentiate and optimize their products.

Implementing low-power configurable processors: practical options and tradeoffs

Configurable processors enable dramatic gains in energy efficiency, relative to traditional fixed instruction-set processors. This energy advantage comes from three improvements. First, configuration of the instruction set permits a much closer fit of the processor to the target applications, reducing the number of execution cycles required. Second, configuring the processor removes unneeded features, reducing power and area overhead. Third, automatic processor generation tools enable logic optimization, signal switching reductions, and seamless mapping into low-voltage circuits and processes, for very low-power operation. The first improvement has been well-studied. Analysis of the second and third improvements requires detailed circuit and layout experiments, which is the primary focus of this paper. Starting from a range of existing available power saving options, this work explores the tradeoff and analyzes the results: the design priority tradeoff, the process technology impact, and implementing low-power configurable processor using commercial scaled-VDD cell libraries compatible with mainstream SOC practices. These real processor designs can achieve power dissipation approaching 20/spl mu/W/MHz at 0.8V and close to 10/spl mu/W/MHz at 0.6V, using production 0.13/spl mu/m libraries. Finally, this work quantifies the dramatic process, voltage and temperature dependence in post-layout leakage power for small processor designs.

Grand challenges in embedded systems

Among the many directions of IT, the most pervasive is the fusion of information processing with physical processes - called embedded computing. It is the basic engine of innovation and source of competitiveness for broad range of industrial sectors from automotive to telecommunications and from aerospace to manufacturing. Embedded computing transforms products, creates new markets and disrupts the status quo. Embedded computing is rapidly taking over the role of being the universal system integrator for physical systems.Prominent leaders of industrial and academic R&D organizations will discuss the consistency between present and future application challenges as seen by industry and dominating research challenges as conceived by academia.

Future systems-on-chip (panel session): software of hardware design?

Advances in device technology have led to an era where entire systems can be implemented on a single component, commonly referred to as system-on-chip. With shrinking product life cycles placing severe time to market demands on manufacturers, coupled with their need to quickly change a products feature set to address evolving customer requirements, programmability will emerge as a corner-stone for all chips implemented in the future. The Internet, communications, consumer electronics, and computing markets are first to take advantage of system-on-chip technology. What are the benefits of programmability to these and other markets and are there potential pitfalls? What architectures and programmability (or reconfigurability) are going to be the likely winners and at what cost? Are these architectures likely to converge or diverge? The panelists will debate the merits of their existing approaches and how they are likely to be shaped in the future.

Are we there yet? Has IP block assembly become as easy as LEGO?

With the majority of chip real estate being filled with re-used IP blocks, the process of block assembly has significantly grown in importance. Marketing literature seems to suggest that assembling a chip from IP is as easy as browsing a library of blocks, assembling them in a block diagram and then pushing a button.

Election year: what the electronics industry needs---and can expect---from the incoming administration

The paper presents a panel discussion from the distinguished members of the electronics industry as they outline the platforms and priorities that the industry would like from the incoming administration of the United States of America. The discussion was framed in a way to help explain what is to be expected from the new administration.