Steve Leibson

Configurable processors: a new era in chip design

Over the past few decades, the microprocessor has emerged as a fixed, stand-alone, reusable block created by highly skilled specialists. Because developing good, efficient microprocessor architectures can take years, many designers have come to regard them as monolithic entities subject to change only over long time periods and after careful consideration by an anointed few. However, the rise of application-specific integrated circuit and system-on-chip (SoC) manufacturing technologies in the 1990s has laid the groundwork for a new, fourth era - that of post-RISC, configurable processors. Configurable processors enable system-on-chip designers to leverage the benefits of nanometer silicon lithography with relatively little manual effort. These processors can achieve much higher performance than processors with conventional fixed-instruction-set architectures through the addition of custom-tailored execution units, registers, and register files as well as specialized communication interface ports.

Flexible architectures for engineering successful SOCs

This paper focuses on a particular SOC design technology and methodology, here called the advanced or processor-centric SOC design method, which reduces the risk of SOC design and increases ROI hy using configurahle processors to implement onchip functions while increasing the SOCs flexibility through software programmability. The essential enabler for this design methodology is automatic processor generation-the rapid and easy creation of new microprocessor architectures, complete with efficient hardware designs and comprehensive software tools. The high speed of the generation process and the great flexibility of the generated architectures underpin a fundamental shift of the role of processors in system architecture.

Extensible and Configurable Processors for System-on-Chip Design

Extensible, configurable, and reconfigurable processor cores mark the start of a new epoch for microprocessors, more suited to SoC design. In this chapter, we present four approaches to achieve higher levels of application-specific performance. Acceleration of a baseline RISC core with a reconfigurable co-processor can provide high performance with a very small amount of configuration data. VLIW DSP approach supporting efficient compiler technology provides a straightforward path for design space exploration and implementation from high-level language entry. An extensible RISC core provides application performance by incorporating new instruction into the instruction set, and finally, a run-time reconfigurable RISC core integrates the application-specific logic into the processor pipeline as a reconfigurable picoGA array

The Future of Nanometer SOC Design

Moores law (double the number of transistors at each new processing node) and classical semiconductor scaling (faster transistors running at lower power at each new processing node) parted company after the 130nm processing node. As a result, on-chip clock rates have stopped rising as fast and transistor power levels have stopped falling as quickly as they did in the past. This change in the trend demands a change to a system-design style that emphasizes the use of multiple processor cores (Leibson, 2006)

Generation and Use of an ASIP Software Tool Chain

Software-development tool chains are hardware-dependent by their nature, because compilers and assemblers targeted to specific processors must generate target-specific code. However, a processor that is both configurable and extensible, with a variable instruction set architecture (ISA) melded to a basic architecture compounds the problems of adapting the software development tools to specific processor configurations. The only tractable way to support such extensible processor ISAs is through a highly automated tool-generation flow that allows the dynamic creation and adaptation of the development-tool chain to a specific instance of the processor. To be of practical use, this process (automated tool generation) must transpire in minutes. This chapter discusses the issues of application-specific instruction set processor (ASIP) configurability and extensibility as they relate to all the elements of a software development tool chain ranging from an integrated development environment (IDE) to compilers, profilers, instruction-set simulators (ISS), operating systems, and many other development tools and middleware. In addition to drawing out the issues involved, we illustrate possible solutions to these hardware-dependent software (HdS) problems by drawing on the experience of developing Tensilica’s Xtensa processor, as an example.

Reduce SOC Energy Consumption through Processor ISA Extension

The combination of reduced core operating voltage and reduced clock frequency achieved through processor core ISA extension greatly reduces the energy required to execute the task, often by one to two orders of magnitude.

Automated Processor Configuration and Instruction Extension

Publisher Summary The application-specific instruction-set processor (ASIP) concept is reviewed in this chapter and discusses automated processor configuration. Tailoring a processor to an application has been more of an art than an exact science, and the process demands effort when done on a manual ad hoc basis. Many existing approaches to ASIP creation require the in-depth knowledge of a processor architect, the software knowledge of applications specialists, and the hardware-implementation skills of a team of experienced digital designers. Both structural, coarse-grained configuration parameters (for example, the inclusion or exclusion of functional units, the width of processor-to-memory or bus interfaces, the number and size of local and system memories), and fine-grained instruction extensions (the addition of application-specific tuned instructions that accelerate the processing of major functional application kernels by a factor of 2 ×, 10 ×, and more) are possible in ASIP configuration. Deciding the specific configuration parameters and extended instructions can be akin to finding the optimal needle in the proverbial haystack—and requires years of broad experience in a host of design disciplines. With this in mind, the design and use of ASIPs on a widespread basis across multiple application domains demand a more automated process for creating these processors from high-level configuration specifications.

Design and verification of complex SoC with configurable, extensible processors

Summary form only given. As SoCs continue to evolve to have more and more programmable elements and processors on them, the opportunity to tune the processors, interconnect and other blocks to match the intended application and gain advantages of performance and energy consumption is one that many designers are still not aware of. Experience on a wide variety of SoC designs has shown that significant increases in SoC performance and reduction in energy consumption are possible through the use of tuned Application-Specific Instruction set Processors (ASIPs), along with the right choices of interconnect structures and associated hardware blocks. This embedded tutorial introduces the audience to the concept of ASIPs and uses practical examples to illustrate how ASIP architectures can be mapped to applications. It also covers a processor-centric design flow for complex SoC and in particular will describe models and methodologies for design, simulation and verification of these devices using the latest electronic system level (ESL) methods.

K-5 Challenges for consumer electronics for the 21st century

CE products now drive the electronic industrys development. (It was previously driven by military programs after World War II, mainframes and minicomputers in the 1950s through the 1970s, and the Personal Computer in the 1980s and 1990s). CE products demand high performance, low cost, and low power consumption. These requirements stress every aspect of design from the circuit to the system level. The tallest technological hurdles lie ahead.

Flexibility and Low Power; A Contradiction in Terms; Can Configurable or Re-Configurable Computing Offer Solutions?

Both configurable computing paradigms as well as re-configurable computing paradigms have gained significant impact within the last few years. Both paradigms have shown to be effective when power consumption is a major design constraint even though the philosophies behind are quite different: configurable approaches aim to adapt an embedded processor to an application through, for example, an extensible instruction set plus other parameters that are determined during design time. They come in two basic flavors: starting with a fixed core that is extended by the system designer or; designing the instruction set from scratch for a specific application. Re-configurable approaches on the other side gain most of their benefits through run-time re-configuration. A high degree of parallelism is needed to overcome the physical deficiencies of re-configurable fabrics (e.g. FPGAs), though. The panel will discuss advantages and disadvantages of these paradigms with respect to low power