Christal Gordon

Floating Gate Synapses With Spike-Time-Dependent Plasticity

This paper describes a single transistor floating-gate synapse device that can be used to store a weight in a nonvolatile manner, compute a biological EPSP, and demonstrate biological learning rules such as Long-Term Potentiation, LTD, and spike-time dependent plasticity. We also describe a highly scalable architecture of a matrix of synapses to implement the described learning rules. Parameters for weight update in the 0.35 um process have been extracted and can be used to predict the change in weight based on time difference between pre- and post-synaptic spike times.

Indirect Programming of Floating-Gate Transistors

Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection. In this indirect programming method, two transistors share a FG allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Additionally, the use of these indirectly programmed FG transistors allows a circuit to be tuned such that the effects of device mismatch are negated. Finally, the concept of run-time programming is introduced which allows a circuit to be recalibrated while it is still operating within its system

Indirect programming of floating-gate transistors

Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection. In this indirect programming method, two transistors share a FG allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Additionally, the use of these indirectly programmed FG transistors allows a circuit to be tuned such that the effects of device mismatch are negated. Finally, the concept of run-time programming is introduced which allows a circuit to be recalibrated while it is still operating within its system

A field programmable neural array

An analog circuit capable of accurately emulating large complex cells, or multiple less complex ones is described. This circuit is termed the FPNA or the field programmable neural array. It is analogous to the more familiar FPGA, but is composed of biologically relevant circuit components including active channels, dendrites, and synapses. Taking each of these circuit models, and adding a routing structure capable of routing outputs from cells (or external inputs) to any individual synapse at any node yields a device which is capable of emulating complex biological circuits. This circuit opens doors to investigating what particular types of computation individual cells are performing, as well as small networks simpler cells

A family of floating-gate adapting synapses based upon transistor channel models

We have developed a family of three analog VLSI synapses based on three types of biological channel types, Ach-excitatory, NMDA-excitatory, and GABA/sub A/-inhibitory in a 0.5 /spl mu/m CMOS process. We have successfully reproduced EPSPs and IPSPs similar to what is found in biology. Presently, we manually modify synaptic strength. We continue our work to expand self-adapting synapses. Since these synapses are relatively small in area, we anticipate having hundreds of them in a single 1.5 /spl times/ 1.5 mm die.

Biological learning modeled in an adaptive floating-gate system

We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptation rules. With increased synaptic activity, the synaptic weights are increased or decreased. That increase or decrease continues with subsequent synaptic activity. This paper explores the relationship between synaptic activity and weight for various inputs We will use our relatively simple network to bootstrap into larger, more complex systems. This system helps to provide insight into intricate natural designs, such as cerebellar cortex. Using the physical properties of our floating-gate pFET device, we are able to re-establish properties seen previously and build upon these first steps. We can modify our learning rule rates and dynamics through capacitively coupled input voltages. Our learning rule has connections to reinforced learning, and therefore may find useful engineering applications.

A floating-gate vector-quantizer

We present a floating-gate based system for computing vector quantization (VQ), which is typically used for data compression and classification of signals to symbols. We present an architecture and resulting circuits which will enable direct programming/storage of weight vectors, as well as methods for adaptive VQ. We use an analog bump circuit to perform a continuous distance computation along a particular input coordinate. Unlike a traditional bump circuit, we use differential floating-gate inputs to provide the ability to store the learned value. The current outputs of each bump circuit are summed along a single wire, where the largest result(s) are selected using a winner-take-all circuit. We present experimental results measured from ICs fabricated on a 0.5 /spl mu/m CMOS process available through MOSIS.

Floating gate synapses with spike time dependent plasticity

This paper demonstrates a single transistor synapse that stores a weight in a non-volatile manner, computes a biological EPSP, and also demonstrates biological learning rules such as LTP, LTD and STDP. It also describes a highly scalable architecture of an array of synapses that can implement the described learning rules. Parameters for weight update in a 0.35µm process were extracted and used to predict changes in weight based on the time difference between pre-synaptic and post-synaptic spike times.