Christopher M. Twigg

Large-scale field-programmable analog arrays for analog signal processing

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.

A Floating-Gate-Based Field-Programmable Analog Array

A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm2 in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.

Automatic rapid programming of large arrays of floating-gate elements

The use of floating-gate elements on analog circuits has increased over the last few years. Floating-gate transistors are been used for analog multiplication, memory storage, on-chip bias, offset removals, etc. Complex systems, such as imagers and filter arrays, use thousands to millions of programmable floating-gate elements. The programming speed and precision of these elements plays a major role on the performance of these systems. In this paper we present a system approach that allows for automatic rapid programming of large arrays of floating-gates. We achieve this by optimizing all the time consuming tasks involved in the programming, such as current measurements and drain pulsing among others.

A Large-Scale Reconfigurable Analog Signal Processor (RASP) IC

The reconfigurable analog signal processor (RASP), one of the first large-scale field-programmable analog arrays (FPAAs), is composed of 56 computational analog blocks (CABs). Each CAB contains various levels of analog computational granularity utilizing over 50,000 programmable analog elements. Bias currents are programmable to within 0.2% from 100 pA to greater than 3 muA. Internal bandwidths are greater than 50 MHz, and the kT/C noise can be adjusted using the drawn capacitances and routing network parasitics. A range of compiled circuits and resulting signal processing systems are presented

Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network

A floating-gate pFET is a desirable switch element for use in a crossbar switch due to it having a resistance on the order of a transmission gate, the capacitance of a single pass-FET, and requires no digital memory to store the state of the switch. As a result, a floating-gate pFET crossbar network can achieve a higher bandwidth than a transmission gate based network. In addition, the resulting floating-gate implementation has a smaller silicon footprint than an array of transmission gates with the necessary support structures. Finally, the resistance of the floating-gate switch is achieved by modulating the input gate voltage during channel hot-electron injection.

RASP 2.8: A new generation of floating-gate based field programmable analog array

The RASP 2.8 is a very powerful reconfigurable analog computing platform with thirty-two computational analog blocks (CABs). Each CAB has a wide variety of sub-circuits ranging in granularity from multipliers and programmable offset wide linear range Gm blocks to NMOS and PMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating gate transistors. This system exhibits significant performance enhancements over its predecessor in terms of achievable signal bandwidth (> 50 MHz), accuracy (> 9 bits), dynamic range (> 7 decades of current), speed of floating-gate programming (> 200 gates/sec) and isolation between ON and OFF switches. The improved bandwidth is primarily due to an improved routing fabric that includes nearest neighbor connections. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Several complex system examples are presented.

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm 2 silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

Application performance of elements in a floating-gate FPAA

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. In this paper, we explore the use of floating-gate devices as the core programmable element in a signal processing FPAA. A generic FPAA architecture is presented that offers increased functionality and flexibility in realizing analog systems. In addition, the computational analog elements are shown to be widely and accurately programmable while remaining small in area.

Developing large-scale field-programmable analog arrays

Summary form only given. Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. We explore the use of floating-gate devices as the core programmable element in a large-scale FPAA with applications in signal processing emphasized. An FPAA architecture is presented that offers increased functionality and flexibility in realizing analog signal processing systems, and experimental data from a testbed FPAA is shown. In addition, mainstream signal processing systems are discussed that can be effectively implemented on large-scale reconfigurable analog devices thereby realizing dramatic savings in power over traditional digital solutions and improved time-to-market over traditional analog designs.

A Floating-Gate-Based Programmable CMOS Reference

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-mum CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of plusmn40 muV . Experimental results indicate a temperature sensitivity of approximately 53 muV/degC for a nominal reference voltage of 0.4 V over a temperature range of -60degC-140degC.