Brian P. Degnan

A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena

We present a single-chip array of 100 biologically-based electronic neuron models interconnected to each other and the outside environment through 30,000 synapses. The chip was fabricated in a standard 350 nm CMOS IC process. Our approach used dense circuit models of synaptic behavior, including biological computation and learning, as well as transistor channel models. We use Address-Event Representation (AER) spike communication for inputs and outputs to this IC. We present the IC architecture and infrastructure, including IC chip, configuration tools, and testing platform. We present measurement of small network of neurons, measurement of STDP neuron dynamics, and measurement from a compiled spiking neuron WTA topology, all compiled into this IC.

Indirect Programming of Floating-Gate Transistors

Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection. In this indirect programming method, two transistors share a FG allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Additionally, the use of these indirectly programmed FG transistors allows a circuit to be tuned such that the effects of device mismatch are negated. Finally, the concept of run-time programming is introduced which allows a circuit to be recalibrated while it is still operating within its system

Hardware and software infrastructure for a family of floating-gate based FPAAs

Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This paper presents the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. This infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA IC, discrete ADC, DAC and amplifier ICs, a 32-Bit ARM based microcontroller for interfacing the FPAA with the users computer, and Matlab and targeting software. The FPAA hardware communicates with Matlab over a USB connection. The USB connection also provides the hardwares power. The software tools include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. The hardware consists of two custom PCB designs which include a main board used to program and control an FPAA IC and an FPAA IC adaptor board used to interface a QFP packaged FPAA IC with the 100 pin ZIF socket on the main programming and control board.

Indirect programming of floating-gate transistors

Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection. In this indirect programming method, two transistors share a FG allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Additionally, the use of these indirectly programmed FG transistors allows a circuit to be tuned such that the effects of device mismatch are negated. Finally, the concept of run-time programming is introduced which allows a circuit to be recalibrated while it is still operating within its system

A 45 μW bias power, 34 dB gain reflection amplifier exploiting the tunneling effect for RFID applications

RFID applications have power constraints that limit RF tags to short range communications. This article presents the design procedures, validated by experimental results, to make a low-powered reflection amplifier that exploits the quantum mechanical tunneling effect to dramatically enhance the range of passive or semi-passive tags. A return gain of 34.4 dB with bias power of 45 μW at 5.45 GHz and a return gain of 22.1 dB with a bias power of 47 μW at 5.55 GHz have been observed for impinging RF power levels as low as -70 dBm. These results allow, for certain devices, a factor of 7 range improvement to the RFID link while keeping the bias power 10 times lower than any other available reflection amplifier. This prototype could play a key role in enhancing RFID communication ranges without significantly affecting the low power budget typical for RFID technology; the design can be implemented in currently available semi-passive tags and opens the door for a new generation of long-range, passive/semi-passive transponders.

Assessing Trends in Performance per Watt for Signal Processing Applications

We present a survey and analysis of processor power efficiency, showing results from the first personal computer until the present day that analyzes the metric of multiply- accumulate (MAC) energy per operation. MAC performance is critical for continued scaling of signal processing applications. We derive our results from published work and published CPU databases, and we hypothesize that a Powerwall exists, above which we do not predict Moores law will bring the current digital computing paradigm. Our results show that this Powerwall exists in a band from 10 to 30 GMAC/W.

Error immune logic for low-power probabilistic computing

Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25µm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

Programmable floating-gate techniques for CMOS inverters

The use of analog floating-gate elements in analog circuit research has steadily increased. These elements have great potential because they can be fabricated on a standard process and are low-power. An interesting application for these circuits is in the tuning of digital circuits for threshold and power consumption, which has been traditionally done by design. We explore the use of analog floating gates for threshold adjustments in a digital inverter.

An asynchronously embedded datapath for performance acceleration and energy efficiency

Motivated by the unwillingness to accept the worst-case timing constraint that synchronous logic imposes, and additionally motivated by finding a supply voltage scaling scheme for datapath circuits that is unconstrained by timing errors in memory elements, the authors have built an asynchronous datapath that is embedded seamlessly into a synchronous register file. This paper will show that not only does asynchronous arithmetic logic exhibit many characteristics that allow it to be inherently lower power, but it is significantly faster than any synchronous counterpart and is a perfect candidate technology for datapath acceleration. Further, novel circuits are presented that allow asynchronous datapath units to be embedded in a synchronous environment with little overhead while the dual-rail asynchronous encoding scheme is successfully converted with equally low overhead. The authors have built a test chip being fabricated at the time of publication. The circuits on this chip will be discussed and simulation results given showing this design to be both energy and performance efficient when compared to other known datapath designs.

Asynchronous trigger modulation for RFID systems

We present a scheme for using asynchronous trigger modulation in radio frequency integrated circuits (RFICs), which allows more robust backscatter modulation without increasing tag power consumption. Since the implementation does not require load modulation transitions that correspond to regular clock intervals of synchronous logic, a whole new class of waveforms in RFID is also possible, including a family of perfect pulses that provide extra sensitivity for long-range tags.