Christian Caillat

Leakage Control in 0.4-nm EOT Ru/SrTiO x /Ru Metal-Insulator-Metal Capacitors: Process Implications

Leakage currents as low as 10^-7 A/cm² at both 1 V and -1 V top electrode bias in the sub-0.4-nm equivalent SiO₂ thickness range are demonstrated in Ru/SrTiO_x/Ru metal- insulator-metal capacitors in which the 8.5-nm SrTiO_x layer is deposited by atomic layer deposition. The top electrode material and deposition technique as well as the postdeposition anneal are crucial parameters to control the leakage, not only at negative, but also at positive top electrode bias.

Endurance of One Transistor Floating Body RAM on UTBOX SOI

Endurance is investigated on one transistor floating body RAM cells processed on a silicon-on-insulator substrate with ultrathin buried oxide, and programmed using the bipolar junction transistor current inherent in MOSFETs. During the hole generation step, defects are generated close to the drain. These defects not only reduce the retention time but also result in a lower hole generation rate as a function of the number of cycles, which leads to a write 1 failure. We have shown that standard junction devices with a lightly doped drain (LDD) region are more enduring than extensionless devices with the LDD left undoped. This is owing to the poor spacer oxide on top of the extensionless region where holes are generated.

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

A new scheme called in the following “Diffusion and Gate Replacement” (D&GR) MIPS integration is demonstrated. The CMOS flow allows to control the gate height asymmetry between NMOS and PMOS by driving the work function shifter directly into the high-k. Since the threshold voltage (Vth) shifter sources are removed, it is compatible with other processes requiring high-thermal budget such as memory technologies (DRAM periphery).

Impact of Al 2 O 3 position on performances and reliability in high-k metal gated DRAM periphery transistors

The impact of the Al₂O₃ position with respect to HfO₂ in the process flow, is investigated. It is shown that Al₂O₃ incorporation in order to increase the pMOS threshold voltage, slightly degrades the mobility, slightly increases NBTI and increases the EOT with respect to the reference without Al₂O₃ Moreover, the trap density profiles depend on the Al₂O₃ position: higher in the interfacial layer when Al₂O₃ is below and higher in the HfO₂ when Al₂O₃ is above HfO₂. Furthermore, Al₂O₃ below HfO₂ shows higher gate leakage, reduced LF noise but marginal NBTI difference compared to AL₂O₃ above HfO₂.

Diffusion and Gate Replacement: A New Gate-First High-

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high-k, and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow.

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In this paper, we propose a method to extract effective diffusion coefficients for Lanthanum in HfO2 for an HKMG technology. TCAD diffusion simulations is combined to the analysis of theoretically expected Work Function shift due to Lanthanum at the HfO2/SiO2 interface and experimentally extracted Work Function value under various thermal budgets, obtaining a good agreement between simulations and experimental data.

/Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry

In this work, the low-frequency noise of UTBOX SOI nMOSFETs developed for Floating Body RAM (FBRAM) applications is reported and compared with the corresponding retention time. A clear trend is shown, relating a high retention time with a low noise spectral density SId. The one decade higher spread in SId compared with retention time indicates that other types of traps are responsible for both parameters. From the fact that for the same noise magnitude a different retention time can be observed in UTBOX nMOSFETs with a different channel processing strongly suggests that besides traps in the silicon film and at the interface, additional factors like the lateral electric field determine hole generation in the Si body.

Understanding workfunction tuning in HKMG by Lanthanum diffusion combining simulations and measurements

In this paper, the feasibility of High-k/Metal Gate (HKMG) Replacement Metal Gate (RMG) stacks for low power DRAM compatible transistors is assessed. It is shown that traditional RMG gate stacks cannot be used because of the additional anneal needed in a DRAM process. New solutions are developed, and a PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a Work Function of 4.95 eV. On the NMOS side, a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/Ta/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated.

On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs

An impact analysis of the various thermal budgets on the electrical trends of a HKMG-Metal Inserted Poly Si gate (MIPS) process through Technology Computer-Aided Design (TCAD) is reported. A good agreement between simulation and experimental data is shown for NMOS and PMOS FETs in a low power and low cost 45 nm technology node. The impact of the C and Ge+C co-implantation on the device performance is explored, with particular emphasis on the effects on the USJ of additional thermal treatments needed by a DRAM compatible periphery. From this understanding, further device tuning can be foreseen, in order to meet specific design requests. An application example of the optimized process simulation is shown, demonstrating the feasibility of different Vth schemes, ranging from low-power to high performance oriented devices.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks

The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation. This paper reviews the main features of GIDL-assisted body biasing and GIDL optimization methods ensuring the best erase effectiveness and variability control. Finally, the excellent reliability of the selector gate devices over Program/Erase cycles is demonstrated, proving the reliability of this technique.