Alessio Spessot

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10-10 A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain from 6T cells. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.

Statistical model of the NBTI-induced threshold voltage, subthreshold swing, and transconductance degradations in advanced p-FinFETs

We study the stochastic NBTI degradation of p-FinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak gm improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of gm aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits.

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels

The self-heating (SH) effect is studied experimentally and through simulations on an extensive set of industry-relevant solutions for FF and GAA-NW Si and high-mobility devices, with multiple processing options. Considerations for managing SH in future technologies are provided.

Low-frequency noise of advanced memory devices

This paper reviews the application of low-frequency noise and Random Telegraph Signal (RTS) studies on advanced memory devices, namely, Metal-Insulator-Metal capacitors with SrTiOx as insulator, peripheral transistors for Dynamic Random Access Memories and Resistive Random Access Memory structures. In the first two cases, flicker noise is used to analyze the quality or defectiveness of the gate stack, while in the third case, both flicker and RTS noise provide information on the carrier trapping and transport.

Low-frequency noise analysis of DRAM peripheral transistors with La cap

In this paper, the impact of the thermal budget on the low-frequency (LF) noise of DRAM peripheral n-channel transistors with La cap implemented in the high-κ/metal gate stack is investigated. Confirmation of previous reports on the beneficial impact of La in-diffusion on the oxide trap density is obtained. At the same time, a peak in the oxide trap profile is demonstrated close to the SiO2/HfO2 interface.

SRAM enablement beyond N7: A BTI study

Operating voltage (Vmin) improvement for High density SRAM with scaling is halted due to variability and aging effects which becomes a bottleneck for energy optimized operation. Device level and cell level advancements help the SRAM in lowering Vmin. Assist techniques become beneficial in Vmin lowering but due to BTI their Vmin degrades. BTI sensitivity analysis for these solutions gives insight of BTI resilient HD SRAM design for advanced technology node.

SRAM designs for 5nm node and beyond: Opportunities and challenges

The rising demand for battery-powered devices is the key driver for continued density scaling and improved power in SoCs. Along with advantages, random VT variation and interconnect RC delay is increased due to the continual scaling of physical dimensions, which seriously degrades SRAM performances, limits VMIN, and makes SRAM less energy efficient. Although FinFET technology can offer a respectable source channel effects (SCEs) and superior VT variation, the competing between channel length (Lg), sidewall spacers, and source/drain (S/D) contacts imposed by contacted gate pitch (CGP) scaling remains unchanged. In this paper, we will present a holistic approach for 6T-SRAM designs using gate-all-around (GAA) transistors, which will firmly address process integrations and circuit aspects arising at the 5nm node. Several read and write assist techniques including wordline (WL) delayed overdrive, VDD collapse and negative bitline (BL) will be exclusively investigated to enable low VMIN and high-performance SRAMs.

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7

As scaling continues for FinFET technology nodes, variability in combination with targeted lower supply voltages results in reduced SRAM stability margins. In this paper, threshold voltage tuning from the technological side is used to enable low SRAM Vmin with minimum impact on logic performance. Furthermore, lower overall system energy consumption can be achieved by the lower Vmin. This exercise is crucial for the enablement of future technology nodes where single VTH masks could become a necessity.