Christian Kromer

A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects

This paper describes a quad optical transceiver for low-power high-density short-distance optical data communication. Each channel transmits 10 Gb/s over a multimode (MM) fiber and features a link margin of 5.2 dB at a bit error rate (BER) of 10/sup -12/. The transmit and receive amplifying circuits are implemented in an 80-nm digital CMOS process. Each driver consumes 2 mW from a 0.8-V supply, and each vertical cavity surface-emitting laser (VCSEL) requires 7 mA from a 2.4-V supply. The receiver excluding the output buffer consumes 6 mW from a 1.1-V supply per channel and achieves a transimpedance gain of 80.1 dB/spl Omega/. The isolation to the neighboring channels is >30dB including the bond wires and optical components. A detailed link budget analysis takes the relevant system impairments as losses and power penalties into account, derives the specifications for the electrical circuits, and accurately predicts the link performance. This work presents the highest serial data rate for CMOS transceiver arrays and the lowest power consumption per data rate reported to date.

A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

This paper describes the design of a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiber-optic interconnect communication system. The single-ended circuit has been designed in an 80-nm digital CMOS process and consumes only 2.2 mW from a 1-V supply. The measured results show a transimpedance gain of 52 dB/spl Omega/ and a large bandwidth of 20 GHz. This work presents the highest bandwidth at the lowest power consumption for CMOS transimpedance amplifiers reported to date.

60 GHz VCO with wideband tuning range fabricated on VLSI SOI CMOS technology

A 60 GHz cross-coupled differential LC CMOS VCO is presented in this paper, which is optimized for a large frequency tuning range using conventional MOSFET varactors. The MMIC is fabricated on digital 90 nm SOI technology and requires a circuit area of less than 0.1 mm/sup 2/ including the 50 /spl Omega/ output buffers. Within a frequency control range from 52.3 GHz to 60.6 GHz, a supply voltage of 1.5 V and a supply current of 15 mA, the circuit dividers a very constant output power of -6.8 /spl plusmn/ 0.2 dBm and yields a phase noise between -85 to -92 dBc/Hz at 1 MHz frequency offset.

A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects

This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of <10-12 and tracks frequency deviations between the incoming data and the reference clock of up to plusmn122 ppm. The sinusoidal jitter tolerance is >0.35UIpp for jitter frequencies les100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UIpp at a BER=10-12. The core CDR circuit occupies a chip area of 0.07 mm2 and consumes 98 mW from a 1.1-V supply

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the chip, which has a compact size of 0.5 mm/spl times/0.47 mm. The circuit covers a radio frequency range from 30 to 40 GHz. At a RF frequency of 35 GHz, an intermediate frequency of 2.5 GHz and a local-oscillator (LO) power of 7.5 dBm, a conversion loss of 4.6 dB, a single-sideband (SSB) noise figure (NF) of 7.9 dB, an 1-dB input compression point of -6 dBm, and a third-order intercept point at the input of 2 dBm were measured. At lower LO power of 0 dBm, a conversion loss of 6.3 dBm and an SSB NF of 9.7 dB were measured, making the mixer an excellent candidate for low power-consuming wireless local-area networks. All results include the pad parasitics. To the knowledge of the authors, this is the first CMOS mixer operating at millimeter-wave frequencies. The achieved conversion loss is even lower than for passive MMIC mixers using leading edge III/V technologies, showing the excellent suitability of digital CMOS technology for analog circuits at millimeter-wave frequencies.

A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1ps at an input frequency of 40GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30mumtimes40mum only

High-Q inductors on digital VLSI CMOS substrate for analog RF applications

In this paper, the design, modeling and performance of high-Q RF inductors using aggressively scaled digital VLSI CMOS technology are presented. Quality factors of 12.7 and 10, and self resonance frequencies of 45 GHz and 29 GHz are measured for inductors with values of 0.31 nH and 0.9 nH, respectively. The influence of parasitics is also investigated.

Comparison of simulation and measurement of dynamic fiber-coupling effects for high-speed multimode VCSELs

Static and dynamic measurements are performed with GaAs oxide-confined vertical-cavity surface-emitting lasers (VCSELs), using multimode fibers with a core diameter of 50 and 62.5 /spl mu/m and different numerical apertures (NAs). They show that a small NA can have a severe impact on the eye opening and thus also on the bit-error rate. The measurements are analyzed with a spatiotemporal two-dimensional (2-D) multimode VCSEL model. The required parameter extraction for the model is verified with small- and large-signal measurements. The analysis shows that the change of the eye opening can be explained by the interaction between the mode- and the current-injection profile, carrier diffusion, and intermodal gain compression (IGC). IGC increases differences in the modal power distribution caused by the interaction between the mode profiles and the current-injection profile. Carrier diffusion is able to compensate these increased differences of the modal power distribution. Its impact, however, on dynamic changes caused by IGC is moderate.

Design of low-power fast VCSEL drivers for high-density links in 90-nm SOI CMOS

The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-/spl Omega/ load. The required chip area is only 140 /spl mu/m/spl times/140 /spl mu/m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than 10/sup -12/ to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model.

Tradeoffs of vertical-cavity surface emitting lasers modeling for the development of driver circuits in short distance optical links

In short-distance optical links, the development of driving circuits for vertical-cavity surface-emitting lasers (VCSELs) requires precise and computationally efficient VCSEL models. A small-signal model of a VCSEL is computationally efficient and simple to implement; however, it does not take into account the nonlinear output behavior of the VCSEL. In contrast, VCSEL models that are highly based on first principles cannot be implemented in standard circuit device simulators, because the simulation of eye diagrams becomes too time consuming. We present another approach using VCSEL models, which are based on the 1-D rate equations. Our analysis shows that they combine efficient extraction and short simulation time with an accurate calculation of eye diagrams over a wide range of ambient temperatures. As different implementations of the rate equations exist, tradeoffs between three different versions are presented and compared with measured GaAs oxide-confined VCSELs. The first model has a linear and the second a logarithmic function of the gain versus the carrier density. The third model considers the additional transport time for carriers to reach the active region with quantum wells. For parameter extraction, a minimum set of parameters is identified, which can be determined from fundamental measurements.